Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
1788 Discussions

Disabling cache coherancy

balu_r_0212
Beginner
‎05-14-2012 04:00 AM
1,013 Views
Is there a way to disable cache coherency in intel sandybridge?
0 Kudos

Link Copied

2 Replies
Patrick_F_Intel1
Employee
‎05-15-2012 07:25 PM
1,013 Views
Hello balu,
You can define a memory region as not cacheable.
Then reads from and writes to that region of memory are not checked for coherency.
Is this what you are looking for?
Pat
0 Kudos
Copy link
balu_r_0212
Beginner
‎05-16-2012 04:28 AM
1,013 Views
Hello Pat,

I was thinking if there is a way to disable MESI protocol (but still take advantage of the cache beingavailable) that is typically used to address "false sharing". Assuming that i guarantee there will be no "false sharing", can i disable the protocol effects (overheads) induced by MESI.

- Balu
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.