hi everyone, I am trying to determine the memory controller configurations of an Nehalem-EX Xeon X7550 processor, such as the open-page mode to close-page mode switching threshold.
Because my BIOS won't tell me much information, I think I need to read the memory controllers' PCI configuration space. However, I have searched the web, and couldn't find any document about the layout of the PCI configuration space. X7550's datasheet mentions a few PCI regeister names, such as M_PCSR_MAP_PHYS_DIMM. But there is no information about the address of these registers and their the data formats. Does anyone know where can I find documents on Intel's PCI configuration space? Or, if the PCI configuration space is not the correct place to look, where can I find information about the memory controller configurations?
Thank you very much.
Intel documents on the Xeon 7500 series that are likely include the information you need are:
- "Intel Xeon Processor 7500 Series Uncore Performance Monitoring Guide", Intel document number 325535-001, March 2010.
- "Intel Xeon Processor 7500 Series, Datasheet, Volume 1", Intel document number 323340-001, March 2010.
- "Intel Xeon Processor 7500 Series, Datasheet, Volume 2", Intel document number 323341-001, March 2010
The second volume of the processor datasheet, in particular, discusses the memory controller configuration.
iliyapolak, Thank you for your reply.
Sorry if this is a dumb question. But, what do you mean by the "PCI specification"? Do you mean the general PCI specifiction? Or do you mean some specifications that are particularly used by Intel? If you mean the Intel specifications, do you have any link to them? I really have no luck finding them.
Also, the system I am using has a X58 chipset. However, it seems X58's datasheet only has PCI configurations for I/O devices. I couldn't find anything related to memory controller. May be I am missing something here?
Hi Dr. McCalpin.
Thank you for the reply. I have read the Xeon 7500 series datasheets. However it does not include any information of the addresses and formats of the PCI registers. For example, it metions a PCI register called M_PCSR_MAP_PHYS_DIMM. But it does not say what is the address of this register, nor does it says anything about the register's format. If I google "M_PCSR_MAP_PHYS_DIMM", there is only one hit on the search, which is the Xeon 7500 datasheet itself.
Any thoughts? Thank you very much.
Intel often restricts the detailed configuration documents to various levels of NDA access.
The specific topic that you raised (open page timers) is one that Intel never seems to publish. I had to devise some fairly sneaky tests to figure out the maximum page open time on my Xeon E3 and Xeon E5 (both Sandy Bridge) systems. I still don't know anything about how the policy varies dynamically.
But... the Xeon 7500 series uncore programming guide provides information on lots of counters that could be used to measure the page open/close behavior. E.g., table 2-78 on page 2-106 describes some memory controller counter control features directly related to counting the various events. A code that repeatedly accesses the same DRAM bank with an adjustable delay between loads could be used to determine the timeout behavior.
>>>iliyapolak, Thank you for your reply.
Sorry if this is a dumb question. But, what do you mean by the "PCI specification"? Do you mean the general PCI specifiction? Or do you mean some specifications that are particularly used by Intel? If you mean the Intel specifications, do you have any link to them? I really have no luck finding them.>>>
Sorry for beign non informative.
I meant PCI Local Bus Specification version 3.0 and you can freely download it in pdf format.
Thank you for the advice, Dr. McCalpin. I was afraid this information is confidential. If it is, then the only solution is to experiment with some micro-benchmarks, like you said. Thank you anyway for the help.