Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Good block diagram of Ivy Bridge architecture

dehvidc1
Beginner
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I'm writing a report for management on how various coding and instruction generation approaches can affect performance and what relevant VTune output means in this context. This reference provides an example akin to what I would like to do albeit in more detail than I plan and with a different focus:

http://www.gamedev.net/page/resources/_/technical/general-programming/a-journey-through-the-cpu-pipeline-r3115

To do the work I need a good block diagram of the Ivy Bridge architecture to display as a figure. This reference has a good diagram:

http://www.euroben.nl/reports/web13/xeon.php

but given I'm doing the work at a scientific research institute I'd like to use a reference from Intel, a book or similar.

I would be grateful if anyone can point me at a diagram of this nature

David

 

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McCalpinJohn
Honored Contributor III
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Ivy Bridge is almost identical to Sandy Bridge, which has its own section in the Intel Optimization Reference Manual (Intel document 248966).  In the January 2016 revision (248966-032) this is section 2.3, with a processor block diagram in Figure 2-5 and lots of related information in Tables 2-12 through 2-24.    A very brief overview of some of the differences between Sandy Bridge and Ivy Bridge is in Section 2.3.7.

For the Ivy Bridge Xeon E5/E7 processors, the chip-level block diagrams are in Chapter 1 of the Uncore Performance Monitoring Guide (Intel document 329468).

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McCalpinJohn
Honored Contributor III
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Ivy Bridge is almost identical to Sandy Bridge, which has its own section in the Intel Optimization Reference Manual (Intel document 248966).  In the January 2016 revision (248966-032) this is section 2.3, with a processor block diagram in Figure 2-5 and lots of related information in Tables 2-12 through 2-24.    A very brief overview of some of the differences between Sandy Bridge and Ivy Bridge is in Section 2.3.7.

For the Ivy Bridge Xeon E5/E7 processors, the chip-level block diagrams are in Chapter 1 of the Uncore Performance Monitoring Guide (Intel document 329468).

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dehvidc1
Beginner
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Thanks for this detailed helpful response, John. The figures in the architecture optimisation manual are what I was after. I spent hours looking through Intel material and other sources but managed to miss that section somehow.

 

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dehvidc1
Beginner
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I used Google when I was looking for the block diagram. As I mentioned above I was unsuccessful using that approach. The keywords in the Document Properties/Description dialog for the Architectures Optimisation Reference Manual .pdf file (recommended by John) are:

intel 64 architecture, IA-32, intel core processors, 248966

The security tab on this dialog reports:

"All contents ofthe document are encrypted and search engines cannot access the document's metadata."

That would go some way towards explaining why my specific Google search was unsuccessful.

This Intel WWW page has a similar block diagram:

https://software.intel.com/en-us/top-down-microarchitecture-analysis-method-win

 

 

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