Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
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How do the match/mask registers work? (for performance monitoring counters)



I'm looking into performance monitoring counters on Icelake SP. One event of interest, M2M PKT_MATCH, requires programming the OPCODE_MM and the ADDR MASK/MATCH registers. The document I'm looking at is "3rd Gen Intel® Xeon® Processor Scalable Family, Codename Ice Lake, Uncore Performance Monitoring", ID 639778.

What exactly does mask/match mean in the context of these registers, for ADDR and for the fields of OPCODE_MM (opc, mc, mcopc)?

  • Does "mask" say which bits of the respective "match" bits should be checked for counting? So e.g. if mask=0b1001 & match=0b0111, would count for all occurences of 0xx1?
    • If this the case, does a mask of 0b000 entail that nothing would match?
  • Or does "match" perform exact matching, while "mask" performs wildcard matching? So e.g. match=0b0110 would only match 0110, while mask=0b0100 would match x1xx.

As it might be apparent, I have some confusion around these terms and their intended usage. Any insight would be appreciated,



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