How to configure Intel FSP-M to get DIMM (DDR5) SPD

[nl_jk]

Hi, 

I am trying to get DIMM (DDR5) SPD. But I can get a partial DIMM SPD (maybe page0). I think that Fsp-m could be configured to get a full SPD. I don't know. 

My test setup: 

Product code: S2EG2SE36Q (Engineering sample)

Serial No. : CSA224800014

platform: Eagle Stream 

Processor: Sapphire Rapids ES2/QS

Board Name: Archer City RP

Phase: Qual

My goal: reading DDR5 SPD and configuring MRC

My test configuration is Coreboot + EDK2, 

Intel FSP is extracted from default BIOS (EGSDCRB1.SYS.WR.64.2022.51.1.02.1552.1_9409.P01_SPR_EBG_SPS_IPClean_Production_Pfr_Container_BtgP0)

.

- how to get DDR5 SPD via Intel FSP, any document.. 

Thanks,

Junkil Ryu

[thismarkjohnson]

FSP-M only exposes what the platform firmware provides, so if you’re only seeing page 0, your SMBus/I3C SPD access isn’t fully enabled in the board init. For DDR5 you need proper I3C SPD support in coreboot and correct FSP UPDs (like enabling full SPD read); Intel doesn’t publish full docs for this outside NDA.

[nl_jk]

I want to know correct FSP UPDs which can enable full SPD read. I think that I can't access I3C SPD (maybe disable (locked) ). can you access it with coreboot?