How to interpret the results of getCyclesLostDueL3CacheMisses and getCyclesLostDueL2CacheMisses

[cagribal]

In the documentation, it says that these methods return a ratio between 0 and 1. What is the exact meaning of this ratio? Also in some measurements, I got a number above 1. How should I interpret it? In documentations there is a note saying that "in some cases could be >1.0 due to a lower memory latency estimation", what does this exactly mean?

Thanks,

[Roman_D_Intel]

The methology to compute this metric is described in these slides. See page 18-19. Asnoted there, it is just a rule of thumb (if >0.2 (20%) it is worth to pay attention to data access pattern of the application). The formulas assume a certain fixed penalty for a miss (access latency in the number of cycles) which in reality may vary from system to system (core clock frequency, DRAM type and speed, how they are populated in the slots, microarch differences, NUMA-locality of accesses, number of sockets 1-2-4-8->8, etc).

Roman