Also, An Altera™ Startix IV FPGA. is placed on the carrier.
Facing a PCIe "no communication" problem when Windows OS starts.
Can anybody draw guidelines for the Power-Up Sequence and/or using the PWR_OK signal and the SYS_RESET# signal?
What is the typical timing for the SYS_RESET#? What is the maximum period of time that a delay before PWR_OK can be set safely?
What should be the length of the pulse of SYS_RESET#?
Thank you very much in advance,
We're not hardware chipset folks on this forum. Did you try the chipset forum?
I note that the chipset spec update talks (see issue 22 "Intel® 5 Series Chipset and Intel® 3400 Series Chipset PCI Express* Link Disable Bit") where the text is:
Problem: Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express* Ports may not exit the disable state when the Link Control Register “Link Disable” bit is set and PCIe Device Electrical Idle Exit is detected.
Implication: Port Specific Software Directed Hot Plug or Power Management support using the “Link Disable” bit may cause an Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express Port to be stuck in the “Link Disable state” until a Host Reset with Power Cycling occurs.
Workaround: For Intel 5 Series Chipset and Intel 3400 Series Chipset PCI Express Port Specific Software Directed Hot Plug or Power Management support, use PCI Power Management Control register D3HOT bits instead of Link Disable bit.
I can't tell if this is the same issue you are seeing.
Chapter 8 of the chipset guide has some timing diagrams but they don't mean much to me.
When you say "Also, An Altera™ Startix IV FPGA. is placed on the carrier.", what does that mean?
It helps - a clue for the direction. I'll search for this Issue 22.
I'd started in the Chipset Forum but has been sent here by the admin. there..
May you can connect me with a "chipset" fellow from Intel that can be the address for my power-up and PCIe link questions?
Thank you very much.