Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Intel Processor Trace

Bogdan21
Beginner
510 Views

I am having a hard time to understand the following text from the SDM (Section 33.3.6):

 

"TSC packets are generated when there is insufficient information to reconstruct wall-clock time, due to tracing being disabled (TriggerEn=0), or power down scenarios like a transition to a deep-sleep MWAIT C-state. In this case, the CYC that is generated along with the TSC will indicate the number of cycles actively tracing (those powered up, with TriggerEn=1) executed between the last CYC packet and the TSC packet. And hence the amount of time spent while tracing is inactive can be inferred from the difference in time between that expected based on the CYC value, and the actual time indicated by the TSC."

 

How exactly can one compute the inactive period? The text "... from the difference in time between that expected based on the CYC value ..." confuses me a lot. Can one give an example?

 

 

0 Kudos
0 Replies
Reply