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Intel Xeon support for Resource Director Technology (RDT)

According to section 17.18 of the Intel Software Developers Manual (Combined Volumes, Sept 2019), Resource Director Technology (RDT) was introduced with the Intel Xeon processor E5 v3 family, the first of which were introduced in Q3 2014.

I just tested CPUID to detect support for Resource Director Technology (RDT) on an Intel Xeon Gold 6140 CPU @ 2.30GHz, and bit 12 comes out zero (no support). Gold 6140 was introduced in Q3 2017.

This is my test (following section 17.18.3 of the Sept 2019 Developers Manual):

mov eax,07H

mov eax,07H

mov ecx,0H


mov r10,12

BT rbx,r10 ; RDT

jnc cont_RDT_99

mov rax,1

mov [rdi],rax


In this case jnc jumps (no carry) so bit 12 is zero (no support).

My questions are:

(1) am I testing CPUID for that purpose correctly? In other words, should Xeon Gold 6140 have RDT support and I'm just not testing it correctly?

(2) is RDT expected to be supported on all Xeon processors after the introduction of the E5 v3 family in 2014, or will some Xeon processors after that time (e.g. Gold 6140) not have support for RDT?

Thanks very much.

UPDATE:  I just tested it on an Intel Xeon Platinum 8175M @ 2.50GHz and that processor also shows bit 12 as zero (following my code above).  Going further, I executed wrmsr like this: 

mov rcx,1
mov rax,0xF
xor rdx,rdx

and I got a segmentation fault, which I assume is because RDT is not supported on this processor. 



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Black Belt

All of my SKX Gold and Platinum and CLX Platinum processors appear to return the same value 0xd39ffffb in %ebx for CPUID leaf 0x7.

Both bit 12 (RDT monitoring supported) and bit 15 (RDT allocation supported) are set in that value.

  • I usually use the cpuid command-line utility from to get these values, or cut-n-paste the relevant bits of C code when I need to execute it inline.  
  • There are four examples of calling CPUID using inline assembly in "low_overhead_timers.c" at
  • There is an example of calling CPUID using the __cpuid() intrinsic (following a Microsoft format) in perf_counters.c at  This version has the benefit of providing all four output registers in an array in a single invocation:
    uint32_t cpuid_return[4];
// The compiler cpuid intrinsics are not documented by Intel -- they use the Microsoft format
// described at
//         __cpuid(array to hold eax,ebx,ecx,edx outputs, initial eax value)
//         __cpuidex(array to hold eax,ebx,ecx,edx outputs, initial eax value, initial ecx value)
// example to get family/model information from leaf 0x01
    __cpuid(&cpuid_return[0], 1);
// mask out the reserved and "stepping" fields, leaving only the based and extended Family/Model fields
    uint32_t ModelInfo = cpuid_return[0] & 0x0fff0ff0;   // array element [0] is eax, [1] is ebx, etc...


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