Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Is L2 Cache Inclusive to L1 Instruction Cache (micro-op cache) in Intel Sandy Bridge?


Is the micro op cache inclusive to L1 Instruction Cache?

Is the L2 Cache Inclusive to L1 Instruction Cache?

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Honored Contributor III

Do you not believe what is written in the architecture docs, not to mention many interesting web pages since Nehalem?

If you have an assignment to look these things up, why are you asking here for answers which you probably need to check anyway?

Where it says loop stream detector keeps decoded micro-ops in Instruction Decoder Queue it seems to imply that the instructions cached in L1I or L2 (with exclusivity) remain coded; besides, the stated limits on size of micro-op queue are far smaller than L1.  It's a lot like the advertisements, "up to" such and such.

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