On a processor that supports L3 CAT (Cache Allocation Technology), assume I create two partitions (P1 and P2). However, I run the instruction "clflush" on an address which should reside in P1 but after switching from P1 to P2. Will "clflush" evict the cache-line in P1 or not?
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Hello AAhma10,
Thank you for contacting us about this concern.
Could you please so kind and provide us more details about the configuration that you are trying to accomplish?
On the other hand, I will double check the information and proceed with the next step in order to provide you the most accurate information.
Best regards,
Emeth O.
Intel Customer Support Technician.
Under Contract to Intel Corporation.
Hello AAhma10,
I am following up your case in order to double check some important details before to proceed with any next step.
Please provide us the model of the processor in which you are trying to accomplish this configuration.
Best regards,
Emeth O.
Intel Customer Support Technician.
Under Contract to Intel Corporation.
Hello,
Thank you for the information provided.
I am going to double check this information with an upper level department in order to clarify the information.
Best regards,
Emeth O.
Intel Customer Support Technician.
Under Contract to Intel Corporation
Hello AAhma10,
For the details you are looking for, I recommend submitting a Service Request following the instructions from the below Developer Zone page since they do not provide support via Intel communities:
How to Create a Support Request at the Online Service Center
https://software.intel.com/en-us/articles/how-to-create-a-support-request-at-online-service-center
Regards,
Pat S.
Intel Customer Support Technician.
Under Contract to Intel Corporation.
