L1 Data Cache in Sandy Bridge

[david42]

These questions are about the 8 banks in the L1 data cache in Sandy Bridge.

Page 3-57 of Intel's Optimization Reference Manual says:
"A bank conflict happens when two simultaneous load operations have the same bit 2-5 of their linear address but they are not from the same set in the cache (bits 6-12)."
http://www.intel.com/Assets/en_US/PDF/manual/248966.pdf#page=183

Page 2-22 of Intel's Optimization Reference Manual says:
"Since 16-byte loads can cover up to three banks, and two loads can happen every cycle, it is possible that six of the eight banks may be accessed per cycle, for loads. A bank conflict happens when two load accesses need the same bank (their address has the same 2-4 bit value) in different sets at the same time."
http://www.intel.com/Assets/en_US/PDF/manual/248966.pdf#page=58

1. Which bits of the memory byte address select an L1 data cache bank?
Since 16-byte loads can cover up to three banks, I guess the data bus of each bank is 8 bytes wide. Bits 0-2 of a memory byte address would select a byte within the width of this data bus. It therefore seems to me that bits 3-5 of a memory byte address select the bank. I don't understand why the Optimization Reference Manual says the bank is selected by bits 2-5 on page 3-57 and bits 2-4 on page 2-22.

2. Do each of the 8 banks in the L1 data cache have a separate read port and write port or does each bank have a single combined read/write port? In other words, can a load and store access different addresses of the same bank in the same cycle?

3. Does an L1 cache bank need some number of idle cycles when switching between a load and a store? If yes, how many?

[Patrick_F_Intel1]

Hello David,
I'm researching the questions.
I'll get back to you soon.
Pat

[Patrick_F_Intel1]

Hello David42,
Thanks for your patience. I've been trying to finish up some work required by the end-of-year.
The correct bit range is 2-5 (the page 183 reference). This will be corrected in the Optimization Guide.
For SNB, there are 2 load ports and 1 store port servicing the whole L1 (not ports per bank).
See, for example, slide 7 of the ppt at http://software.intel.com/file/32266 or the optimization guide section 2.1.
Loads and stores can access the same bank (different addresses)in the same cycle.
Lastly yes, there are 'a few' idle cycles when switching between a load and a store. I'm told not to be more specific than 'a few'.
Hope this helps,
Pat

[david42]

Thanks for your efforts while you have other work that you're trying to finish. According to the Optimization Reference Manual, the L1 data cache in each core of Sandy Bridge has 8 banks (page 2-22). It only takes 3 bits to select one of 8 banks. How can bits 2-5 select the L1 cache bank since bits 2-5 are 4 bits?

You say "Loads and stores can access the same bank (different addresses) in the same cycle." If that's true, why would there be idle cycles when switching between a load and a store to a bank?

Did you mean loads and stores can access different banks (not the same bank) in the same cycle? If there needs to be a few idle cycles when switching between loads and stores to a bank, that sounds like each bank has a single read/write port. In other words, it is not possible for a load and a store to access the same bank in the same cycle.

[Patrick_F_Intel1]

Hello David42,
For the first part: although there are only 8 banks the Opt Guide correctly says A bank conflict happens when two simultaneous load operations have the same bit 2-5 of their linear address but they are not from the same set in the cache (bits 6 - 12). So a bank conflict can happen for 2 simultaneous loads of the same 4-bytes (relative to the cache line) for cache lines in different sets.

For the second part (starting with You say), I should have said: SNB can read and write different banks at the same cycle.

For part 3:
1) Did you mean loads and stores can access different banks (not the same bank) in the same cycle?
a. Yes.
2) For the rest of the questions, were not going to disclose any more information than we already have.

I hope this helps,
Pat