PMC 0x48, umask 0x1 (L1D_PEND_MISS.PENDING) incrementsthe number of outstanding L1D misses every cycle.
The counting probably starts as soon as an L1D miss occurs and before a buffer is allocated for the miss.
The L1Dmiss might require a trip to L2 or L3 or memory. I suspect that it counts bothcacheable and uncacheable memory accesses.
L1D_PEND_MISS contains an unknown mix of types of misses.
So you can't use it to compute an L2->L1 miss latency.