Measuring MCT read/write request, how to in PMC

[perfwise]

Hi,

I'd like to measure the read and write MCT requests on Sandybridge but don't find these documented on line in the PMC documentation. Can someone please inform me if it's available or suggest how one should measure the stats on hardware. I'd like to do so on my SB system.

I already have the L1D, L1I, L2 and some of the L3 stats (which are also not documented in great detail). Thanks for any help.

perfwise

[perfwise]

Can anyone at Intel tell me how to measure memory IO in terms of PMCs? I think this would be something you do commonly.. at least from the user perspective it is definitely something users care about. Any help is greatly appreciated.

perfwise

[Roman_D_Intel]

Hi perfwise,

I am not aware of memory read/write request statistics for memory controller available through performance monitoring units on Sandy-Bridge mobile/desktop processors. What you can do is to try approximate processor-originated request statistics using the UNC_CBO*L3 events available in the uncore PMU. This method however has a little insight into how much memory traffic is caused by streaming (non-temporal) writes, external (PCIe) devices or graphics.

Best regards,

Roman

[Patrick_F_Intel1]

Thanks Roman,
The uncore performance counter architecture on Sandy bridge processors changed quite a bit.
We are working to provide more uncore counter access but at this point in time I can't say when this will be.
Pat