Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

PCIe wire latency from RC to EP on Xeon Haswell



I'd like to know an estimate of the latency between the Root Complex (RC) and an Endpoint (EP) on a Haswell machine (Intel(R) Xeon(R) CPU E7-8867 v3 @ 2.50GHz). Could someone provide me with this latency or point me towards how to possibly measure it?

I am making a model for the latencies involved in sending a message from a sender node to a receiver node; the PCIe wire latency is a missing part.

Thank you,
Rohit Zambre
Ph.D. Student
University of California, Irvine

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