PCIe wire latency from RC to EP on Xeon Haswell

Software Tuning, Performance Optimization & Platform Monitoring

Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

PCIe wire latency from RC to EP on Xeon Haswell

320 Views

Hi,

I'd like to know an estimate of the latency between the Root Complex (RC) and an Endpoint (EP) on a Haswell machine (Intel(R) Xeon(R) CPU E7-8867 v3 @ 2.50GHz). Could someone provide me with this latency or point me towards how to possibly measure it?

I am making a model for the latencies involved in sending a message from a sender node to a receiver node; the PCIe wire latency is a missing part.

Thank you,
Rohit Zambre
Ph.D. Student
University of California, Irvine

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.