PMC accronyms.. what do they stand for..

[perfwise]

Hi,

I am trying to understand the PMC purposes in the Intel System Guide 2 so as to measure the PMC performance on my SandyBridge cpu. Can someone tell me what:

IQ (as in PMC 87H)

PMH (as in PMC 85H)

MITE (as in PMC 79H)

DSB (as in PMC 79H)

PBS (as in PMC C2H)

LBR (as in PMC CCH)

also.. looking at the definition of:

PMC F0H mask 20H: L2_TRANS.L2_FILL

are these fills to the D$ or I$ that are serviced by the L2.

Similarly for:

PMC F0H mask 20H: L2_TRANS.L2_WB

are these writebacks to the L2 from either the D$ or I$?

Lastly.. if there is any outline of where these resources are in the pipeline of my SandyBridge.. that would also be useful.

Thanks..

[Patrick_F_Intel1]

Hello Perfwise,
After talking to more folks, I realized the answer is there in the optimization guide.

The manual says The event IDQ_UOPS_NOT_DELIVERED counts when the maximum of four microops are not delivered to the rename stage, while it is requesting micro-ops. When the pipeline is backed up the rename stage does not request any further micro-ops from the front end.

So, when there are cache misses (back end stalls), the rename stage is not requesting uops and so the front-end is not delivering uops and so this counter doesnt increment.

The methodology in sections B.3.2-B.3.7is intended to be used in sequence.
First determine if you are front or back end stalled (section B.3.2) and then, if you are front end stalled, use section B.3.7 to further analyze the workload.
Or, as the manual puts it:
B.3.7 Front End Stalls
Stalls in the front end should not be investigated unless the analysis in Section B.3.2
showed at least 30% of a granularity being bound in the front end.

Sound reasonable?
Pat