PMU events for Cannonlake

[Travis_D_]

I can't find the definitions for the PMU events for Intel's Cannon Lake architecture. It's not at https://download.01.org/perfmon/, nor in the most recent version of the Intel SDM.

Chips that were released later, like Cascade Lake (CLX) have already been uploaded to the above link, but no signs of Cannon Lake?

In the absence of the official documentation, can we get some hints as to what architecture the PMU most resembles?

[McCalpinJohn]

Section 19.3 of Volume 3 of the SWDM groups Skylake, Kaby Lake, and Coffee Lake together, so there is not a lot of change from the client side.  The 01.org entries show very little difference between SKX and CLX, so not a lot of change from the server side either.

Comparing the SKL and SKX files from 01.org shows very few differences:

• SKX has Event 0x28 CORE_POWER license cycles
• SKX has the AVX512 umasks for Event 0xC7 FP_ARITH_INSTRUCTION_RETIRED
• SKX has Event 0xD3 MEM_LOAD_L3_MISS_RETIRED that only makes sense in multi-socket systems
• SKX has Event 0xEF CORE_SNOOP_RESPONSE -- may be unique to the SKX mesh?
• SKX has Event 0xFE IDI_MISC.WB_* -- unique to the non-inclusive L3 in SKX

The only Cannon Lake processor I see is https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3_20-GHz, which is a 2-core processor, so it is probably a good start to assume the same coherence protocol as the client parts, but with the AVX512 extensions for Event 0xC7. 

[Travis_D_]

McCalpin, John wrote:

Section 19.3 of Volume 3 of the SWDM groups Skylake, Kaby Lake, and Coffee Lake together, so there is not a lot of change from the client side.

Right, but we know those are all the same microarchitecture, with perhaps minor bug fixes - so I wouldn't expect anything about the PMU architecture to change. Cannon Lake is a new architecture, with perhaps significant modifications to the core: for example, I measure many more available oustanding misses from L1, so the LFB system has apparently been reworked.

The 01.org entries show very little difference between SKX and CLX, so not a lot of change from the server side either.

Comparing the SKL and SKX files from 01.org shows very few differences:

• SKX has Event 0x28 CORE_POWER license cycles
• SKX has the AVX512 umasks for Event 0xC7 FP_ARITH_INSTRUCTION_RETIRED
• SKX has Event 0xD3 MEM_LOAD_L3_MISS_RETIRED that only makes sense in multi-socket systems
• SKX has Event 0xEF CORE_SNOOP_RESPONSE -- may be unique to the SKX mesh?
• SKX has Event 0xFE IDI_MISC.WB_* -- unique to the non-inclusive L3 in SKX

The only Cannon Lake processor I see is https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-C..., which is a 2-core processor, so it is probably a good start to assume the same coherence protocol as the client parts, but with the AVX512 extensions for Event 0xC7. 

Yes, that's the only one I'm aware of and the one I'm using.

At least empirically most Skylake events seem to work, but I'm hoping for an official update at some point.

[McCalpinJohn]

Nice -- other than KNL, there has not been a change in the LFBs for a long, long time.....