I am a grad student whose research is mainly about memory hierarchy. To understand the latest eDram cache architecture in Haswell (e.g. i7-4770R) more, I was trying to use PMC to verify some detail in this paper: http://computingnow.computer.org/cms/Computer.org/ComputingNow/issues/2014/06/mmi2014020006.pdf. However, according to the Software Developer’s Manual, Ch. 19-3, there is no performance-monitoring event that is directly related to eDram cache. Is that just because the manual has not been updated? Or there is no such thing for eDram, and I have to measure performance metric for eDram by combinations of L3 stats and main memory stats?
Thanks for any help in advance.
>>>Software Developer’s Manual, Ch. 19-3, there is no performance-monitoring event that is directly related to eDram cache. Is that just because the manual has not been updated?>>>
What is your latest revision of SDM?
The performance monitoring events in Chapter 19 of Vol 3 of the SW Developer's Guides are mostly limited to the core performance counters. Only a small number of processors have descriptions of uncore performance monitoring events in Chapter 19, and the eDRAM in the Haswell systems (aka, "Crystal Well") is definitely part of the uncore.
Table 19-5 in Section 19.3 does contain a small number of uncore events for some Haswell processors (06_3CH and 06_45H), but the Crystal Well system that I am running on now is a different model (06_46H). I don't know if all Haswell processors with eDRAM have the same DisplayModel_DisplayFamily signature that my system has.