Skylake has a number of improvements that should provide increased cache throughput. It is very common for there to be a tradeoff between unloaded latency and throughput under load. Spreading cache lines across the four slices of the L3 cache will increase the latency, but will also increase the worst-case throughput considerably by decreasing conflicts for L3 access. Nothing new here....
Skylake also has significantly higher frequencies than Haswell in the lower power bins (e.g., 35W), and it is possible that latency tradeoffs were made to enable some of these power reductions. One common case where latency and power conflict is in speculative access to the next level of cache. If you don't care about power you can start L3 accesses in parallel with the L2 access & thereby reduce the average latency in the event of an L2 miss. The lowest latency comes with the highest power consumption, and vice-versa.
