Software Tuning, Performance Optimization & Platform Monitoring
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Specification difference of L1 instruction miss event between Broadwell and Cascadelake


Hi, Let me some questions about specification of L1 miss performance counter ofBroadwell-EP and Cascadelake-SP.

I want to compare L1 instruction Hit/Miss counts of Broadwell-EP and Cascadelake-SP by collecting performance counters. Icache.misses event Broadwell supported looks unsupported in Cascadelake-SP, and following events are added in Cascadelake-SP.

1. Which event is the same as Icache.misses?
2. Please let me know the difference between the use of ICACHE_64B.IFTAG_MISS and FRONTEND_RETIRED.L1I_MISS.
3. Is ICACHE_16B.IFDATA_STALL equal to L1I Cache miss penalty?
4. Is the Icache.misses (Event 0x80, UMASK 0x02) event collectable in Cascadelake-SP?

Ref: Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B:System Programming Guide, Part 2 Order Number: 253669-072US May 2020

Best regards.

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