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The invariant TSC should only change frequency if the 100 MHz reference clock changes frequency. Since this is generated outside the processor, the processor temperature should not have a direct impact. (There will be an indirect impact if the processor heats up the entire motherboard, of course.)

The amount of temperature-induced drift of this reference clock will depend on the quality of the implementation. For a clock that is going to be used for the PCIe interface, the PCIe standard specifies that the clock must be accurate to within 300ppm, so the worst case allowable would be +/- 0.03%.

If I am reading the datasheets correctly, clock generators for Intel processors are typically specified to have an accuracy of no worse than 100 ppm, or +/- 0.01%.

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The invariant TSC should only change frequency if the 100 MHz reference clock changes frequency. Since this is generated outside the processor, the processor temperature should not have a direct impact. (There will be an indirect impact if the processor heats up the entire motherboard, of course.)

The amount of temperature-induced drift of this reference clock will depend on the quality of the implementation. For a clock that is going to be used for the PCIe interface, the PCIe standard specifies that the clock must be accurate to within 300ppm, so the worst case allowable would be +/- 0.03%.

If I am reading the datasheets correctly, clock generators for Intel processors are typically specified to have an accuracy of no worse than 100 ppm, or +/- 0.01%.

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Ok, thanks John!

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