Will we ever see an update to IACA to account for changes in instruction latencies, uop and port breakdowns on Skylake? Currently it only supports up to Haswell, but several things of note have changed in Skylake, and it can produce quite incorrect results if you are using say the variable shift operations like VPSLLVD.
Skylake has been out for a couple years at this point, and the next chip iteration (Kaby Lake) is already out so it seems overdue for an update.
If Intel has abandoned this tool entirely, can it at least be released as open source? I'm sure the community (including myself) would be willing to keep in updated, at least approximately.
IACA is really awesome when prototyping kernels. It is not a substitute for real world testing with vtune or some other PMC-using tool, but neither are those tools substitutes for the uop breakdown, critical path analysis and port pressure analysis that IACA does.
Huh, well to answer my own question (at least in principle), at the bottom of the IACA page there are some comments, and the last one by Israel Hirsh (Intel employee) says:
we are resuming support for Intel(R) Architecture Code Analyzer with BDW and SKL support probably before end of 2016. a few bug fixes, incl. missed zero idioms may be expected. no ETA for VTune integration, possibly will never happen.
So it seems like we might be in luck?