What is the relationship between PMU and PEBS for intel CPU?

[Nan_X_1]

I know for intel CPU families, there are PMU(Performance Monitoring Unit) and PEBS(Precise Event Based Sampling). What is the relationship between them? Per my understanding, the PMU contains PEBS, is it right?

[Thomas_W_Intel]

PEBS is a feature of the PMU.

The PMU can be used in two modes:

1. Counting. This is what Intel Performance Counter Monitor or Likwid are using. For example, it counts how many cache misses occured.
2. Sampling. This is what Intel VTune Amplifier XE or Linux Perf are using. The PMU is used to take samples, when an events has occured a certain number of times. For example, one collects samples after 1M cache misses.

PEBS is an extension of "sampling". The PMU is instructed to collect additional information if a sample is taken. For example, the precise instruction counter, registers or flags are recorded.

[drMikeT]

Is PCM using any heuristic to reconcile counter values in the platforms were the PMU may not count correctly the events?For instance, in SB the flops are counted multiple times on an L1 cache-miss while the pipeline is re-issueing the op-code? Can we find any more concise explanation of how these are handled by PCM?

thanks

Michael

[Roman_D_Intel]

Hi Michael,

Metics in PCM use validated PMU events. There is no metric in PCM that uses FLOPS events.

Thanks,

Roman