Our group is facing a difficult issue from insufficient memory bandwidth. In our computer vision system, we have a frame grabber that DMAs images to memory at ~5GiB/s. The processing use close to the remaining bandwidth in a 2 socket Xeon server.
The frame grabber then occasionally overflows as a result.
Ideally, I'd like to know if there's a way to tell the memory controller to give priority to reads/writes from the PCIe fabric over those from the cores?
Having done some software overclocking, I know there’s a wealth of low level configuration registers to tweak in things like the memory controller, PCIe root complex, as described here
I’ve went through that but there was little to suggest a priority can be assigned to PCIe reads/writes (did find a reference to credit based flow control for DMI traffic, but DMI is only for low bandwidth I/O devices).
thanks for any help,
-Yale
