Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

intel xeon hardware cache events not supported


I am trying to use perf tool to measure performance on some program. For some reason perf stat doesn't support hardware cache events. I'm using intel xeon e5-2620 (haswell) processor. I read in some thread in this forum that the event codes might have been changed for this cpu and that is why perf doesn't support these events. I tried using perfmon2 to find the raw events but with no luck.

Does anybody know how to find the correct raw events for hardware cache events for this cpu?

I'm specifically interested in L1-dcache-loads and L1-dcache-stores but a generic solution will be better. I am using Linux version 3.0.101-0.47.52-default.


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Black Belt

The hardware performance counter events for all Intel processors (except Xeon Phi) are documented in Chapter 19 of Volume 3 of the "Intel 64 and IA-32 Architectures Software Developers Manual: Volume 3 (3A, 3B, & 3C): System Programming Guide" -- Intel document 325384.  The latest revision is 055, from June 2015.   In this revision, the events for the Xeon E5 v3 are contained in Tables 19-6 and 19-9.

It is very difficult to figure out what "perf stat" has decided to use for the various named performance counter events, so I only use the raw event descriptors.   The events that I use for L1 Data Cache Loads (Event 0xD0, Umask 0x81) and L1 Data Cache Stores (Event 0xD0, Umask 0x82) have not changed from Sandy Bridge to Ivy Bridge to Haswell to Broadwell, and the documentation says that they will still be the same on Skylake.

It is always a good idea to check the processor "specification update" documents to see if there are known errata for the various performance counter events.  For the Xeon E5 v3 (Haswell) processors, this is Intel document 330785, revision 007, June 2015.   I don't see any errata listed for these performance counter events.

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