no-fill mode in sandy bridge

[le_g_]

Hi every one,

     I found that the no-fill mode(cr0.CD=1 cr0.NW=0) did not work in my prosessor(i7 2600). Specifically, when I access a memory region that is surely in the L1 Dcache after entering the no-fill mode, the speed suffers significantly(*1000+). But according to table 11-5 in intel SDM vol 3A, read hit should access cache. And I am sure that I have the correct memory type(WB in the experiment, both is mtrr and pat) and the process is restricted in a single core with intertrupt disabled.

     In fact, when in the no-fill mode, everything becomes slower. In my experiment, simply movl %eax,%ebx takes a lot of cpu cycles. Can any one give me some explaination?

     Thanks.

[Patrick_F_Intel1]

Hello Le G,

Here are some snippets from Dr. Levinthal's opus http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf

"The L1D miss creates an entry in the 16 element superqueue and allocates a line fill buffer."... "When all the line fill buffers are in use, the data access operations in the load and store buffers cannot be processed. They are thus queued up in the load and store buffers. When all the load or store buffers are occupied, the front end is inhibited from issuing uops to the RS and OOO engine."

Clearly the fill buffer is intimately connected with the efficient transfer to/from L1D. When you disable the fill buffers, it sounds like the chip behaves as if all the fill buffers are in use (but I'm speculating about that behavior).

I'm reminded of the old joke "Doctor, when I do THIS it hurts!", and the doctor says "then don't do that".  I'm sorry to not provide more information but it takes a lot of time to track down the experts and ask them to respond. Then the experts will say, "Why would anyone disable the fill buffers? That is not the correct operating mode of the processors. Tell them to enable the fill buffers. I don't have time to answer all the infinite ways you can slow down the processor. If there is a problem with the performance of the processor in normal operating mode then we'll work on it."

Sorry to not be more helpful,

Pat

[le_g_]

Hi, Mr Fay,

      Thanks for your quick reply.

      You are right that I set the CPU into an unnormal state and this mode is not guaranteed to work very quickly. But as stated in my original post, even if the cpu works without the memory, the speed still suffers. So I can infer that it's not cache as well as fill buffers that limits the speed, but some thing that I can not think out. 

Patrick Fay (Intel) wrote:

Hello Le G,

Here are some snippets from Dr. Levinthal's opus http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf

"The L1D miss creates an entry in the 16 element superqueue and allocates a line fill buffer."... "When all the line fill buffers are in use, the data access operations in the load and store buffers cannot be processed. They are thus queued up in the load and store buffers. When all the load or store buffers are occupied, the front end is inhibited from issuing uops to the RS and OOO engine."

Clearly the fill buffer is intimately connected with the efficient transfer to/from L1D. When you disable the fill buffers, it sounds like the chip behaves as if all the fill buffers are in use (but I'm speculating about that behavior).

I'm reminded of the old joke "Doctor, when I do THIS it hurts!", and the doctor says "then don't do that".  I'm sorry to not provide more information but it takes a lot of time to track down the experts and ask them to respond. Then the experts will say, "Why would anyone disable the fill buffers? That is not the correct operating mode of the processors. Tell them to enable the fill buffers. I don't have time to answer all the infinite ways you can slow down the processor. If there is a problem with the performance of the processor in normal operating mode then we'll work on it."

Sorry to not be more helpful,

Pat