As far as I know, all of Intel's cache allocation control technologies work by restricting the number of "ways" of the cache that can be accessed for a particular QoS class or access type. For example, DMA writes to system memory are cached in 1 or 2 "ways" of the LLC. The mapping of address to CHA slice and to set within the CHA is unchanged, but the cache is effectively direct-mapped or 2-way set associative for those transactions.
Section 17.19.2 of Volume 3 of the Intel Architectures SW Developer's Manual supports this general understanding of how Intel's Cache Allocation Technology works, but notes that the implementation may differ from a simple 1:1 mapping:
It is generally expected that in way-based implementations, one capacity mask bit corresponds to some number of ways in cache, but the specific mapping is implementation-dependent.
