Exceed recommended operating condition

[Altera_Forum]

Hi, 

 I'm sorry for making a very low level question.  If input signal level of FPGA exceeds the recommended operating conditions, i.e. higher than 3.6V, what will happen? Increase jitter? Input buffer timing is not guaranteed? or something else?  Thanks,

[Altera_Forum]

Permanent chip damage must be feared, particularly with recent 65-nm technology, used e.g. for Cyclone III. See the detailed discussion of allowable voltage overshoot in Cylone III Device Handbook and AN 447.

[Altera_Forum]

FvM, 

 Thank you very much for your answer, but is it true for case not violating absolute rating and exceeding recommended operating conditions?  Thanks,

[Altera_Forum]

My guess would be that you would take the device outside of its operating spec - i.e. your timing might be affected, it could get too hot eventually, draw too much current etc. 

 I think the absolute max ratings means that permanent damage will occur if you take the voltage to that point at all - i.e. if you take the input above 3.6 V temporarily then the device might not work properly but when you take the voltage back down below 3.6V then it will behave as normal. If you were to take it even briefly past the absolute max then the device might / is likely to suffer permanent damage.  If you continually operate the device outside of the recommended range then you may eventually damage the device but I don't know this for sure; or for how long you'd have to run to do this.  If you're desparate to know then I'd raise a query directly with Altera - I assume that you're asking out of interest - i.e. not because you're planning on designing with the device operating beyond its recommended limits - I think you'd be on thin ice doing that.

[Altera_Forum]

--- Quote Start ---  but is it true for case not violating absolute rating and exceeding recommended operating conditions?  --- Quote End ---   This question sounds rather theoretical to me, at least in case of a 3.3V I/O standard. Typically you get some additional overshoot, and should rather worry about violating the maximum ratings. In case of the the single ended I/O standards, I wouldn't expect particular problems, if you manage to stay precisely in the maximum rating intervall. I guess, there are much more designs out there, that don't actually keep maximum ratings and still work. As a simple mean of reassurence, many designers simple don't measure some critical signals...  Recommended operating conditions can be expected as an issue with differential I/O standards, e.g. keeping the common mode range or the differential voltage level. I have seen e.g. LVDS receivers still working without a termination resistor. But it's very unlikely that the timing specifications are still maintained in this case.

[Altera_Forum]

Hi FvM and batfink, 

 I appreciate explanation. I also asked Altera directly and the answer is overshoot exceeding recommended input voltage level is no problem as far as not exceeding absolute range specs.  Regards,