Trying to invoke Fast Input Registers in ID?

[Altera_Forum]

Hi, 

I'm trying to bring in an 18 bit data bus into the top level of an Incremental Design and have the output then feed into a partition that's right up against it. In the top level the input bus is just continuously clocked at 200MHz (50/50 duty cycle clock from an EPLL), no enables or anything. I did declare the registers as Fast Input Registers in the Assignment Editor. The partition is right up against those pins. The design compiles okay but I get 16 warnings that 16 of the 18 bits  Warning: Can't pack node fpa_data_in_a[15] to I/O pin   Warning: Can't pack node fpa_data_in_a[15] and I/O cell a_out[15] -- connection from the combinational output port on the I/O cell to the logic cell is assigned the Decrease Input Delay to Internal Cells delay chain logic option   Using help to hunt this down I get;  CAUSE: You assigned the Decrease Input Delay to Internal Cells delay chain logic option to the connection from the combinational output of the I/O cell to the register cell, and also assigned the Fast Input Register logic option to either the I/O cell or the logic cell. A Decrease Input Delay to Internal Cells delay chain option on a connection implies that the connection must drive out of the I/O cell and therefore is inconsistent with placing the destination register inside the I/O cell.   ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, change the Decrease Input Delay to Internal Cells delay chain logic option on the connection from the I/O cell and the logic cell to a Decrease Input Delay to Input Register delay chain logic option, or remove either the Fast Input Register logic option or the Decrease Input Delay to Internal Cells cell delay chain logic option.     Huh, no I didn't and I can't find where this is invoked in the Assignment Editor to change it as suggested. Any suggestions?:o

[Altera_Forum]

Okay, I didn't get any feedback on this but I did experiment for a while and got it to work. Its kinda weird that one type of I/O register usage must be done at the top level yet another, similar but not same, usage must be done at the lower level (?).

[Altera_Forum]

How exactly did you solve this problem. I am having a very similar type of problem.