Dynamic Bus sizing problem with narrow master and wide slave

Altera_Forum · ‎07-17-2010

Hi,

In my sheme an avalon master is connected to SDRAM slave in the SOPC builder. Both are 16 bit wide.

When the master's clock is 25MHz and SDRAM clock is 100MHz writes from master to SDRAM are duplicated. For example a byte write from master to a location in SDRAM is duplicated with a second one writing to all the 16 bits.Reads are OK.

Everything is fine when both master and slave are operating at 100Mhz.

Both 100Mhz and 25Mhz clocks are derived from a 50MHz input using PLLs.

I am using Quartus II 6.1 for the prject.

I am tempted to believe that the multi clock logic in the Avalon Switch Fabric is misbehaving.

Any ideas about what the problem could be?

Thanks in advance for any help.

Altera_Forum · ‎07-26-2010

This to update that the problem got solved by setting "Extarct Verilog State Machines" setting to OFF. This thread can be considered closed. Thanks to all.