I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

[Altera_Forum]

I have a DK-DSP-3C120N KIT,the NIOS II clock can not exceed 100mhz.The highest speed of NIOS II /f is now just 100mhz.The C program always dead when the clock exceed 100mhz.I want to working at least 166.667mhz,can anybody help me? 

My workshop is Quartus II 9.0 & NIOS II 9.0.

[Altera_Forum]

Are you meeting timing when you re-compile for a higher speed? Also are you constraining your design? 

 Reaching 167MHz is possible on Cyclone III but I wouldn't expect to get it running any faster than that. Instead of cranking the CPU clock speed up I would invest some time looking for bottlenecks and determining what exactly needs to run fast. Then you can optimize or offload algorithms into dedicated hardware. This should result in lower power, more processing efficiency, and typically more scaling (once you hit the limits of the silicon you can't turn up the clock speed anymore).

[Altera_Forum]

Thank you for reply.I'll study how to meeting the timing and constraining my design.After TimeQuest timing analyzer,I find some unconstrained paths: 

Illegal Clocks 0 0 Unconstrained Clocks 1 1 Unconstrained Input Ports 3 3 Unconstrained Input Port Paths 67 67 Unconstrained Output Ports 13 13 Unconstrained Output Port Paths 13 13   I don't know how to add the constrain in the synthesis.

[Altera_Forum]

This design should get you started: http://www.altera.com/support/examples/nios2/exm-c2h-mandelbrot.html 

 It targets the Nios II kit which uses the same base board. If you search around on the Nios wiki you'll probably find a couple other designs that target the same base board with Timequest .sdc constraints.  When constraining the input and outputs you need to specify minimum and maximum delays which take off-chip trace delays and external IC timing constraints like Tsu, Th, and Tco into consideration. Some I/O may be slow and asynchronous to your system in which case you may be able to 'cut' those paths. Some I/O are also multi-cycle which you can set multi-cycle constraints for. If you do all of the above then you should end up with no un-constrained I/O.  Here are some other good docs to read:  http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf http://www.altera.com/literature/an/an433.pdf?gsa_pos=5&wt.oss_r=1&wt.oss=source%20synchronous

[Altera_Forum]

In order to constrain the I/Os,I must specify the max/min input and output delays.But how to decide the max/min value? Should I get it from the Electrical Characteristics in the CycloneIII Handbook? 

Thank for BadOmen.

[Altera_Forum]

Nope they are based on board trace delays and the timing of the devices connected to the FPGA. The output delays are based on trace delay and the setup and hold times of the external device. The input delays are based on the trace delays and min/max clock to out times of the external device. Typically the datasheets will only define the maximum clock to out (Tco) and you can assume the minimum is 0. 

 What I'm describing are called "system centric" constraints. The FPGA data sheet approach that you are referring to is called "FPGA centric" constraints. Both work but I recommend the system constraint approach since it's less work and less error prone.  I forgot to mention these examples: http://www.altera.com/support/examples/timequest/exm-timequest.html

[Altera_Forum]

Thank for your suggestion.The clock and I/O constraint is now correct.But my sopc system still have 63 unconstrained path. 

In order to test the highest speed of NIOS II based on EP3C120N780C7,I construct a simplest sopc system which only using a NIOS II/f CPU,ALTPLL(50mhz in,100mhz,166.7mhz,2.5khz(seg7led clk) out),Timer,JTAG,ON-Chip RAM and a seg7led driver IP for display the status of the C program running. The NIOS II C program is normal at 100mhz system clk,but always dead when the sytem clk exceed 100mhz(125mhz,150mhz,166mhz). The uncontrained path is the only limit to the speed? The SOPC builder automatically generates a .sdc constraints file,I build another .sdc file for clk and I/O,all this .sdc file was add to the project,But the TimeQuest analysis still report 63 unconstrained path,I don't know how to resolve these path .   (from)altera_reserved_tdi (to)asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[0] altera_reserved_tck  altera_reserved_tdi asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[15] altera_reserved_tck  altera_reserved_tdi asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[35] altera_reserved_tck  altera_reserved_tdi asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[37] altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9] altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0] altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10] altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0] altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] altera_reserved_tck  altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled altera_reserved_tck  altera_reserved_tdi sld_hub:sld_hub_inst|irsr_reg[6] altera_reserved_tck  altera_reserved_tdi sld_hub:sld_hub_inst|jtag_ir_reg[9] altera_reserved_tck  altera_reserved_tdi sld_hub:sld_hub_inst|node_ena[1]~reg0 altera_reserved_tck  altera_reserved_tdi sld_hub:sld_hub_inst|node_ena[2]~reg0 altera_reserved_tck  altera_reserved_tdi sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] altera_reserved_tck  altera_reserved_tdi sld_hub:sld_hub_inst|tdo_bypass_reg altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|hub_mode_reg[0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|hub_mode_reg[1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][2] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][3] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][4] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][2] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][3] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][4] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|node_ena[1]~reg0 altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|node_ena[2]~reg0 altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|reset_ena_reg altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][2] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][3] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][4] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][2] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][3] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][4] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|virtual_dr_scan_reg altera_reserved_tck  altera_reserved_tms sld_hub:sld_hub_inst|virtual_ir_scan_reg altera_reserved_tck

[Altera_Forum]

Thank you very much,BadOmen! The NIOS II/f is now working on the 166.7mhz system clock.I just constraining the input clock,altpll and seg7led I/O port obey your suggestion.But the TimeQuest still report mass unconstrained paths: 

--1)Setup Analysis: Unconstrained Input Ports:(1)altera_reserved_tms:No input delay, min/max delays, or false-path exceptions found; (2)altera_reserved_tdi:No input delay, min/max delays, or false-path exceptions found. totally 63 unconstrained paths. Unconstrained Output Ports:(1)altera_reserved_tdo:No output delay, min/max delays, or false-path exceptions found. totally 1 unconstrained paths.   --2)Hold Analysis: The unconstrained paths are the same as above.   I wonder at the NIOS II/f is working under so many unconstrained paths.  How to clear these unconstrained paths? What's the altera_reserved_tms,_tdi,_tdo meaning?

[Altera_Forum]

tms, tdo, tdi, and tck are the JTAG pins. If you have a .sdc file open you can open up the Quartus II templates menu option and go to the Timequest templates. There should be one for JTAG that shows a generic set of constraints to use on those pins.

[Altera_Forum]

Dear BadOmen: 

For the JTAG Signal Constraints,I've added the following code in my .sdc file:# JTAG Signal Constraints constrain the TCK port create_clock -name tck -period 100.000 [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -group [get_clocks tck]# Constrain the TDI port set_input_delay -clock tck 20.000 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock tck 20.000 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock tck 20.000 [get_ports altera_reserved_tdo]   When I "Read SDC File" in the TimeQuest,It always report "Error Status" in the SDC File List.I found only this sentence cause the error:  set_clock_groups -group [get_clocks tck]  Why? It seemed has no syntax error. The file status turn to OK when I delete the sentence,but can not constraining the JTAG.

[Altera_Forum]

Oops sorry I forgot that issue with the template. The template will be fixed in the next version I think. Try this instead: 

 set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms] set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]  Using 1 is overkill since the dev kits don't have that much board delay, I just picked it at random.

[Altera_Forum]

Thank you,BadOmen! 

Your codes are working.All unconstrained paths has been cleared! After Report All Summaries,the report pane of TimeQuest display 2 red warning: 1)Summary (setup)  Clock slack end point TNS inst|the_altpll_0|altpll1|pll3|clk[0] -1.167 -131.807  2)Summary(recovery) inst|the_altpll_0|altpll1|pll3|clk[0] -5.900 -78.992   To constraining PLL,I place this code in the .sdc file: create_clock -name {clk_50mhz} -period 20.000 -waveform { 0.000 10.000 } \[get_ports {clk_50mhz}] derive_pll_clocks derive_clock_uncertainty   The input clock of the altpll is 50mhz,and output clock is 166.7mhz I don’t understand where the negative slack come from,and how to eliminate it.  After compilation ,I receive 3 critical warning(Timing requirements not met) because of this.

[Altera_Forum]

The setup failures are probably real timing violations. You are using a -7 speed grade so it might be difficult to hit 167MHz depending on your design. I would scale that clock down to 150MHz then start optimizing from there. 

 Recovery failures have typically come having the PLL instantiated within my SOPC Builder system. This is a result of a clock crossing adapter being placed in front of the PLL slave port. I normally instantiate my PLLs outside of SOPC Builder for this reason. A recovery failure is similar to a data setup time violation only instead of data it has to do with the reset of a flip flop.... I hope that makes sense, I'm not very good at explaining timing analysis. Using the latest SOPC Builder I have noticed fewer cases where recovery/removal timing violations occur during analysis.

[Altera_Forum]

Thank you for your help.The negative slack and critical warning has been dismissed. 

Scaling the PLL down to 150MHz according to your idea also get setup failure(in slow 1200mv 85c model).So I was compelled to give in to the 133.333MHz,and then all right. The slow 1200mv 85c model Fmax=142.29MHz, The slow 1200mv 0c model Fmax=152.63MHz. I wish to work stable in 133.333MHz clock which can synchronous to the DDR2 SDRAM---my next objective.

[Altera_Forum]

Dear BadOmen: 

Recently,I'm struggling with the DDR2 HP Controller under the direction of AN517(Using High-Performance DDR, DDR2, and DDR3 SDRAM With SOPC Builder).The design is targeted to the Cyclone® III EP3C120F780C7 Kit.   In this example,the SOPC system contain a Half-Rate DDR2 Controller working at 150MHz(altmemddr_auxfull),the PLL of the controller simultaneously generate a 75MHz output clock(altmemddr_sysclk) which been used as SOPC system clock.   After compilation,I got three critical warning again------also cause by JTAG.The TimeQuest report negative slack(-2.428) in Summary(Removal) of altera_reserved_tck.   I lose my head of this because I've constrained the JTAG using the templet:# JTAG Signal Constraints constrain the TCK port create_clock -name tck -period 100.000 [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo] I didn't know what's wrong with it.  An other problem is the unconstrained path cause by the reset_n(cpu reset pin).My constraint code below this: set_input_delay -add_delay -max -clock [get_clocks  {inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|pll|altpll_component| auto_generated|pll1|clk[0]}] 2.0 [get_ports {reset_n}] set_input_delay -add_delay -min -clock [get_clocks  {inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|pll|altpll_component| auto_generated|pll1|clk[0]}] 1.0 [get_ports {reset_n}]   In my mind,the reset_n should be constrained by the system clock(altmemddr_sysclk,75MHz),I got it's name from the Clocks Summary of TimeQuest.   But in the compilation warning,the constraint code was ignored assignment because the Argument -clock is an empty collection.  It means the clock name was wrong.  How can I get the correct system clock name generate by the PLL of DDR2 HP Controller?

[Altera_Forum]

Try this:  

derive_pll_clocks -create_base_clocks set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]  set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]  set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]  set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]   The first line will make sure that there is a clock called 'altera_reserved_tck' in your system and the last three lines will be constrained with respect to this clock.   Usually I set these long clock names to short names names using variables. Then you can refer to the variable using $<variable name>  set Short_Name <really long hierarchy name for signal/clock>  Since reset_n into the system must be held low for a two or more cycles I normally cut the reset_n input pin. On the dev kits the reset_n signal is hooked up to a push button so the reset will occur for many cycles. Inside the SOPC Builder system reset_n is synchronized to each clock domain in your system. Usually I don't attempt to tackle recovery/removal timing violations until my design meets setup and hold times and all my I/O are constrained. Usually the recovery and removal timing violations can be resolved by additional constraints around the reset synchronization logic.

[Altera_Forum]

Hello,BadOmen: 

Thank you for reply. As your suggestion,I add this code in the .SDC file: set sys_clk inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[0]   I'm not sure if it has no syntax error.The TimeQuest still warning like this:   1:Warning: At least one of the filters had some problems and could not be matched.  --- Warning: sys_clk could not be matched with a clock.   2:Warning: Ignored assignment: set_input_delay -add_delay -max -clock [get_clocks {sys_clk}] 2.000 [get_ports {reset_n}] --- Warning: Argument -clock is an empty collection   3:Warning: Ignored assignment: set_input_delay -add_delay -min -clock [get_clocks {sys_clk}] 1.000 [get_ports {reset_n}] --- Warning: Argument -clock is an empty collection   The long clock name which I got from the clock summary seemed incorrect: inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[0]

[Altera_Forum]

You declare variables using 'set <var name> <value>' but when you use the variable in your script you have to use '$<var name>' 

 i.e. set Imavariable abc $Imavariable > abc

[Altera_Forum]

Thank you for your prompt. 

The constraining on resrt_n is working,all unconstrained paths has beed cut.   But the critical warning cause by JTAG still exist. The TimeQuest report negative slack(-2.435) in Summary(Removal) of altera_reserved_tck.  The Top Failing Paths (Removal:altera_reserved_tck) is this: Slack:-2.435 From---altera_reserved_tck  To-----pzdyqx:nabboc|pzdyqx_impl:zdyqx_impl_inst|FNUJ6967  I've tried to slow down the DDR2 clock to 133.333MHz,the NIOS clock down to 66.667MHz,but the slack value still negative.   The constrainning code: derive_pll_clocks -create_base_clocks  set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]  set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]  set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]  set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]

[Altera_Forum]

I don't have a good story for that one because that is the open core plus logic. Open up Timequest and have it report the worst failing paths. Then copy and paste those paths into a text file and either attach it to this thread or send it to me in a private message and I'll take a look. This logic is used to hold your logic in reset after a timeout if you disconnect the programming cable and use an IP core in OCP mode.

[Altera_Forum]

Thank your guidence! 

Here is the .txt of the worst failing path,also include some warning reported by TimeQuest because of cpu.sdc file.