I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

[Altera_Forum]

I have a DK-DSP-3C120N KIT,the NIOS II clock can not exceed 100mhz.The highest speed of NIOS II /f is now just 100mhz.The C program always dead when the clock exceed 100mhz.I want to working at least 166.667mhz,can anybody help me? 

My workshop is Quartus II 9.0 & NIOS II 9.0.

[Altera_Forum]

Those warnings about keepers not being matched are fine. That just means the constraints are in place but the logic is not present in the final hardware image. I need to see the worst failing paths. In timequest there is a macro available that'll list the top failing paths. It'll probably be limited to 200 paths but I need to see the top few otherwise I can't tell what paths need additional constraints. The listing will have the to and from nodes as well as the launch and latch clocks (both should be the JTAG clock). I typically don't need to constrain these paths since I have all the necessary IP licenses which avoids the open core plus logic. In your design the open core plus logic has this name: "pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967" and is generated only when you do not have a valid license for the ip in your system. From compile to compile I'm not sure if that logic name stays constant which could make it difficult to constraint.

[Altera_Forum]

Hello,BadOmen: 

The report of the Top Failing Paths has only one item.I could not see any more failing path in the TimeQuest report.

[Altera_Forum]

Hi,BadOmen: 

When I add the Full Rate DDR2 SDRAM High-Performance Controller with ECC option,the Total Memory Interface DQ width must be set to 72bit,and the local interface width become 128bit.I don't know how to deal with the 32bit NIOS ii cpu.Than you.

[Altera_Forum]

Hello, 

 I am designing an Ethernet connectivity using Cyclone III development board, therefore RGMII is used as an interface between the MAC & PHY.  After building the complete system in SOPC builder and then compiling the design, there are a lat of warnings and a critical warning (timing requirement not met).  I am trying now to fix the critical warning. In doing so, I started by constraining all paths and I/O ports in the design, the number of warnings decreased, but there is still a critical warning (timing requirement not met).  Any advice regarding this issue.  Thanks & Regards

[Altera_Forum]

After running the Read SDC, I noticed that somehow it creates the altera_reserved_clk with the same name, altera_reserved_clk, This can be seen by Running "Report Clocks" on the Diagnostic section. 

 There fore I uncoment the generation of the clock from the template, and change the references from tck to altera_reserved_tck. # create_clock -name tck -period __period [get_ports altera_reserved_tck]# Cut all paths to and from tck  set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 20 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 20 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 20 [get_ports altera_reserved_tdo]   This is at least constraining the altera paths, however I am not tottally sure if this is correctly contrained, I would like to know if it is correct.  I hope someone find this usefull. Thankyou

[Altera_Forum]

Hello vlsidc (http://www.alteraforum.com/forum/member.php?u=28388):tms, tdo, tdi, and tck are the JTAG pins. BadOmen said the template will be fixed in the next version I think. Try this instead: 

 set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms] set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]  Using 1 is overkill since the dev kits don't have that much board delay, I just picked it at random.------BadOmen.     I've eliminate critical warning (timing requirement not met) in my final sdc file,like this:   derive_pll_clocks -create_base_clocks   set altera_reserved_tck {altera_reserved_tck}   set_clock_groups   -exclusive   -group [get_clocks $altera_reserved_tck]   -group [get_clocks "$ddr2bot_auxhalf_75 $ddr2bot_sysclk_150"]  -group [get_clocks "$ddr2top_auxhalf_75 $ddr2top_sysclk_150"]  # jtag interface set_input_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tms ] set_input_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tdi ] set_output_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tdo ]  ---good luck!

[Altera_Forum]

--- Quote Start ---  Thank you for your help.The negative slack and critical warning has been dismissed. Scaling the PLL down to 150MHz according to your idea also get setup failure(in slow 1200mv 85c model).So I was compelled to give in to the 133.333MHz,and then all right. The slow 1200mv 85c model Fmax=142.29MHz, The slow 1200mv 0c model Fmax=152.63MHz. I wish to work stable in 133.333MHz clock which can synchronous to the DDR2 SDRAM---my next objective.  --- Quote End ---    I am suffering from the same critical warning regarding the timing requirement not met.  I am implementing an Ethernet connection on Cyclone III development board. All clocks, inputs & outputs are constrained. I tried to decrease the system clock to 133.333 (as you suggested), but still having this critical warning  Can any one help me in this issue.  Thanks & Regards

[Altera_Forum]

Hello vlsidc: 

If you are using the MegaCore Function in your design,like DDR2 High Performance Controller or Triple Speed Ethernet,you should have all the necessary IP licenses. The critical warning regarding the timing requirement not met maybe cause by the IP license. In my design the open core plus logic has this name: "pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ69 67" and is generated only when you do not have a valid license for the ip in your system. I'm disturbing by this trouble for a long time till I spend heap dollars on the licenses. Then the nios/f is working fine under 133mhz with the full speed DDR2,tse and others.