AVMM address mapping

[UserID4331231]

Hi Every one 

I am using Agilex 7 device and using R-TILE PCIe DMA IP example design.

In the platform designer I can see that PCIe dut block has "bam_master" AVMM Master port. In PCIe end point configuration I have chose 256MB of BAR 0.

While looking at signal of "bam_master" AVMM Master port I noticed following things.

1. Address signal is 28 bit wide.
2. read data and write data signals are 512 bits wide.
3. Byte enable signal is 64 bit wide.

I am wondering how 258MB address range is used by Master port. with above configuration 

total addressable space is  2**28(address lines) = 256M  + each AVMM transaction can handle 64 bytes of data , so  256M * 64 =  16GB is total addressable memory space.

I also tried experimenting with on chip memory IP. here I tried creating 8K memory with S1 port width 64.  Here the memory IP got generated with following  AVMM agent port configuration

1. Address signal is 10 bit wide.
2. read data and write data signals are 64bits wide.
3. Byte enable signal is 8 bit wide.

here this configuration adds up to 8K addressable memory. total addressable space is  2**10(address lines) = 1K  + each AVMM transaction can handle 8 bytes of data , so  1K * 8 =  8KB is total addressable memory space. 

SO, I am confused on how address mapping is working on AVMM master and AVMM agent ports.

please help.

[RichardTanSY_Altera · Accepted solution]

For AVMM master (we have rename this as host) port:

When you mentioned that you set BAR0 Size = 256MB for the PCIe end point configuration, this means the PCIe endpoint exposes 256MB of addressable space to the host system.

The host can perform reads/writes within this range.

With the AVMM Master Port Address Width = 28 bits, this allows the AVMM master to generate addresses from 0x00000000 to 0x0FFFFFFF, which is exactly 256MB of addressable space. [2^28 = 268,435,456 bytes = 256 MB] So the address space matches the BAR0 size.

With Data Width = 512 bits (64 bytes) , each AVMM transaction can transfer 64 bytes of data at once. However, this does not multiply the address space—it just increases the bandwidth per transaction. 64 bits Byte Enable allows fine-grained control over which bytes in the 64-byte data word are valid during a read/write.

For AVMM slave (agent) port:

Address Signal Width = 10 bits (2^10 =1024) This means the AVMM agent can decode 1024 addresses.

Data width = 64 bits (8 bytes) Each address points to a 64-bit word, not a single byte. So1024 * 8 bytes = 8192 bytes (~ 8Kb)

With 8 bits Byte Enable, this allows selective access to individual bytes within the 64-bit word.

For further details on the Avalon® -MM Agent Addressing, you may checkout this user guide:

https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/mm-agent-addressing.html

Additionally, Platform Designer supports auto base address assignment for Avalon® -MM components. In the Address Map tab, click Auto Assign Base Address.

Regards,

Richard Tan

[RichardTanSY_Altera]

Hi,

Any update on this?

Regards,

Richard Tan

[UserID4331231]

I understand the above solutions and I was able to establish address conversions table based on above information. I also validated a few transactions with use of STP. Thank you for your help

[RichardTanSY_Altera]

Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed. 

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan