a question about verilog hdl?

[Altera_Forum]

i have a question about this below: 

is there some differences betwen if (a == 0) and if (!a),I tried a number of simple examples, no difference. Do you think so?

[Altera_Forum]

Doubtfull. By difference, do you mean a difference in functionality, or a difference in area/speed(but same overall functionality). Synthesis does a good job of optimizing most structures, which gives you leeway to code in what makes the most sense. Of course, it does such a good job the final results often aren't what you'd expect, i.e. you may ask why/how it optimized something to such a degree, but once you spend a lot of time analyzing it, you realize the synthesis is correct.

[Altera_Forum]

--- Quote Start ---  Doubtfull. By difference, do you mean a difference in functionality, or a difference in area/speed(but same overall functionality). Synthesis does a good job of optimizing most structures, which gives you leeway to code in what makes the most sense. Of course, it does such a good job the final results often aren't what you'd expect, i.e. you may ask why/how it optimized something to such a degree, but once you spend a lot of time analyzing it, you realize the synthesis is correct.  --- Quote End ---   i mean is there some differences between them in synthesis? for me ,i didn't find any difference.thx!

[Altera_Forum]

What is a? Which differences do you expect? I expect no differences, cause both expressions are functionally identical by Verilog specification, either for a bit or a vector.  

 Discussing possible synthesis results is meaningless without considering the following action, I think. If you set e.g. two registers depending on the comparison result, not all bits of a (assuming it's a vector) may be evaluated by identical LUTs due to optimisation.

[Altera_Forum]

--- Quote Start ---  What is a? Which differences do you expect? I expect no differences, cause both expressions are functionally identical by Verilog specification, either for a bit or a vector.   Discussing possible synthesis results is meaningless without considering the following action, I think. If you set e.g. two registers depending on the comparison result, not all bits of a (assuming it's a vector) may be evaluated by identical LUTs due to optimisation.  --- Quote End ---   a maybe a input signal ,or a reg variable, or a wire variable. i think there is no difference between them when i judge whether a variable is equal zero. THX for reply!

[Altera_Forum]

I hope there's no difference, because I use them both interchangeably, depending on whichever one I think makes the code more readable.

[Altera_Forum]

As FvM suggested, the only difference in the synthesis can arise if using the same condition to perform two (or more) different operations. 

In this case the best practice is to try to optimize the code from the beginning by selecting in the condition (a==0) the minimum number of bits of a that, being equal to zero, guarantee the required condition. In this way you certainly optimize the synthesis.

[Altera_Forum]

For the case you are looking at (a == 0) vs !a, it is likely the synthesis tool will optimize to the same thing in the end. 

 However, I have seen a performance increase when comparing two signals using  !(a ^ b) vs. (a == b)  The performance increase comes at the expense of using one more LUT.  Jake