- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello, how can I combine a verilog file and a *.bdf (Schematic) file ? I know that I could create a symbol file of my *.v file and deposit it into the *.bdf file. Is that the only possibility ?
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes. I think this is the only way to do it. Another way is you can convert bdf to hdl file and use hdl in your top module.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page