成功了! 订阅已添加。
成功了! 订阅被移除。
很抱歉,您必须验证才能完成此操作。请单击您电子邮件中的验证链接。您可以重新发送,通过 配置文件.
Hello, how can I combine a verilog file and a *.bdf (Schematic) file ? I know that I could create a symbol file of my *.v file and deposit it into the *.bdf file. Is that the only possibility ?
链接已复制
Yes. I think this is the only way to do it. Another way is you can convert bdf to hdl file and use hdl in your top module.