Hello,
I have a design with a main clock of 100 MHz. With a clock divider I made a clock enable for about a 9 MHz (clock). The 9 MHz will be used to control and LCD. The data which needs to be send to the LCD is sorted in a FIFO.
The FIFO I generated don't has a clock enable. I think this is normal. But how do I used the read side of the FIFO with the about 9 MHz clock. Is it save to connected the clock enable to the read clock of the FIFO? Or is there a beter way to use the FIFO with the clock enable? I think I can use the rdreq of the FIFO but the process which is reading the data of the FIFO is clocked a 100 MHz with the clock enable of 9 MHz. So if I clock the read side of the FIFO to the 100 MHz clock and the read process is clock via the 9 MHz clock enable, the rdreq will be to long active (this way I will lose data).
Thanks
PS there is no possibility to make the 9 MHz clock with a PLL in my design!! Board issue and the PLL outputs I'm using are generating other clock frequencies.
