Incorrect behaviour of DSPBuilder 7.1SP1 block SinglePulse in hardware

[Altera_Forum]

Hello everyone, 

 we dicovered an incorrect behaviour of the DSPBuilde block SinglePulse when we integrated it in a QuartusII design and brought it to our StratixII FPGA.  Our environment is QuartusII/DSPBuilder 7.1SP1 on WinXP platform.  We are trying to generate a Pulse with a lenght of serveral clocks (in our case 12). But the generated pulse has just a length of one clock for any case when we complied the design with SignalCompiler added it to another QuartusII project and analyzed the signals with SignalTapII. As a simulink model the design works fine. We also get this behaviour when we create a test design containing just a singlepulse connected to an output pin...  Has somebody of you discovered this issue before?  Is this problem related to the "incorrectly connected counter block" as it is described in the DSPBuilder 7.1SP1 Errata Sheet? I would be happy if anybody could give me an idea how to fix this?  Thanks, Bernhard

[Altera_Forum]

Could you post the very simple design you mentioned (just to be sure there's no misunderstanding)?

[Altera_Forum]

Sorry for my late reply, I was out of office the last days. 

 Attached to this post you can find a TestPulse.zip which includes the DSPBuilder model and all generated files ... (our environment is DSPBuilder 7.1SP1, QuartusII 7.1SP1, Matlab 2006b)  In order to test the generated code we opend the quartusII project that was created by DSPBuilder in the corresponding subfolder. We also attached SignalTapII logic to it within quartus, so the quartusII project was modified after it's gerneration with SignalCompiler.  I hope we can get an idea what is going wrong with this example design.  Thanks, Bernhard