Are QII7.1 Symbol files mandatory ?

[Altera_Forum]

Im struggling to rework a simple MaxII design I created two years ago ....and I first found a bug in the first hour of working ...support was good got back and told me the next(new) Serv Pack solved the problem of crashes when editing symbol files !! So ever onward and I cannot seem to get bus ports assigned to my symbol for the macro functions I create using schematics/blocks in the design file. 

If the block and table I/O are mapped and names inside and out correlate in width and names (even) whay wont the damn thing compile ...what else does it need to know ??? Some speedy advice would earn my everlasting adoration !!!

[Altera_Forum]

Drop the symbols and the schematics and go straight HDL code. 

 In the Spring, all will be good in the garden (name that movie)

[Altera_Forum]

Avatar ...I havent the time to worry about DHL,TCL,Verilog or the remainder of the rubbish ! I should be able to use a simple graphics design and all I am trying to achieve is a simple I/O expansion for a dumb microprocessor ..any other design with schematics sub blocks would save my problem ...I just need to see ONE simple design that tells me how to get the node/bus/conduit from a schematic subblock thru to a master block and Ill be fine ...I've read the idiotic help system and I have not SEEN ONE example project of similar simplicity !!! Im really annoyed at the time its taking to do this simple task ! This thing is the PITTS:mad:

[Altera_Forum]

Wow, 

 It is not my intent to make you upset or mad.  I have been designing since the 70's, starting out on punch cards, etc. Worked my with the best of them through the schematic days, andfor the longest time I was a schematic's rule person.  Kicking and screaming, I worked my way through PALASM, ABEL, CUPL, AHDL, VHDL and Verilog.  In the end, not having to resolve all the issue that come up over and over again with various symbol based compilers that just don't seem to ever get the into's and out-of's correct, let alone the inout-of's, I have found that just writing some simple Verilog code with all the Inout's only at the top level gets t he job done!  You asked for some help that would earn my everlasting adoration, and I offered it.  These tools are supposed to make our life easier. That's my advise.  Sorry it rubbed you the wrong way.

[Altera_Forum]

Not mad at you Avatar ...I did Palasm->ABEL->CUPL + a bit of TCL. I built a graphics compiler for DSP stuff and grew to respect the circumspect of graphics ...but this crud drives me nuts ...I discovered the same bug AGAIN in QIISp0...and am now trying to download 650MBytes of new bloatware to be saved (?) by Sp1. 

In QII7.1SP0 the bug on creating sym files was more extensive than just port alterations on the symbol image !! If ANY change is done in an underlying Graphics design file the new generation/update of symbol file from the design file window simply zeros the I/O on the updated block file in the next level up !!  How could they miss this gross error and release V7.1 !!   They gotta start getting high level views when they design biggie PLDs ...so Im for graphics and expert system foundations on this gear .... A lot better than the old hot PALs huh !

[Altera_Forum]

As is a problem with schematics, I don't follow what you're describing. You have a lower level schematic(with Input/Output ports), have created a symbol(hopefully letting Quartus do that for you), and have placed it up a level and are hooking up the ports in the symbol? Naturally, that should work fine, so it sounds like something is being done that hasn't been captured by the description(or that I'm not following). A picture being worth a thousand words, can you attach a project showing this? I assume you don't want others to see your final project, so maybe just a quick dummy design?

[Altera_Forum]

Thks Rysc ...but I have finally gotten the whole thing to compile ...my problem that took a DAY to work out was that I thought I shouldnt use pins in sub - blocks ....I didnt realise the compiler ignores them until gets to top level block. 

This is not stated anywhere explicitly that I could find ... and I think its a dumb idea anyway ..they should have a special block I/O symbol. Dont you think ? Or am I still up the creek ?  Anyway friend ...thks for the care.

[Altera_Forum]

Understood. I've been burned the other way. I was using(I think Simulink) and using top-level ports to create/connect symbols rather than the primitive that is dedicated for that. I don't think there's a right/wrong way. I do like the Altera schematic way though, in that you can point to any level of hierarchy in the design and make it your top-level, to see how it compiles on its own, and you don't have to modify it by adding "top-level ports".  

 I thought there were Quartus schematic examples as a category at: http://www.altera.com/support/examples/exm-index.html But don't see them. Yet if you click on by product examples for Max and Max II CPLDs, there appear to be graphical examples. (I haven't looked at them)

[Altera_Forum]

I looked at the examples ...they were all .v and megafunction where the symbol blocks were already made ....I needed an example of SIMPLE home made sub-block symbol file creation..couldnt see one anywhere ...its was VERY frustrating.. 

I need to sleep ... may the force be with you.............