Send and receive bit in one clock

[Altera_Forum]

Hi !! 

 I am designing SPI interface between FPGA and Encoder.Here on Slave side, i have only 3 port (One is for clock, 2nd is for select slave and 3rd is for data, internally have MOSI and MISO port but externally connected with Transistor so i have only 3 port)..On master side, i am making 4 port (one is for sending bit to slave (MOSI), 2nd is receiving bit from slave to master(MISO), 3rd is clock and 4th is slave..here for data transmission on master side, i will connect externally one transistor between MISO and MOSI.)  Now my question is, How can i send bit from master to slave and recieve bit from slave to master in one clock..  If suppose i will use..   Clock'event and clock = '1' then it might be collison bit sending and receiving bit on same clock coz i have only one data line between slave and master. (if suppose, i have 2 data line then its not a problem)  Any idea how can i send and recieve one bit in one clock ?? or any new suggestion about .. ??  Thanks a lot..

[Altera_Forum]

Why can't you use another pin? The SPI interface is specifically designed to use a minimal amount of pins, i.e. 4. If it could have easily been done with 3, I'm sure it would have. I think the straightforward answer is that it's not possible, as you can't have two drivers on a single line. Now, you could probably time multiplex them, so that you know one signal drives first, is captured, and the other drives so much later and is captured so much later that they don't interfere, but you're basically trying to sneak two signals into one clock. You could use rising and falling clock edges for this.