Audio CODEC AIC23 vhdl/verilog

[Altera_Forum]

Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any controller or IP for controlling this audio codec. I am just wondering does any of you guys have any Verilog/VHDL example codes to control this audio codec. If you do not have then could you please direct me somewhere from where I will be able to get it. Your help would be highly appreciated. Thanks.

[Altera_Forum]

Hi EOFZ, 

Is that the audio attached file can be use for cyclone III dsp development kit? There is also the same audio codec AIC23.  Is that I just need to change the pin location? But i face some timing problem "Time requirements not met"

[Altera_Forum]

Hi EOFZ, 

"Time requirement not met " is solved. but i face  Critical Warning: Ignored Power-Up Level option on the following registers  Critical Warning: Register command_gen:u_command_gen|stop_flag will power up to Low.  How can i solve this problem? I using Cyclone III. tks.

[Altera_Forum]

Your design tries to implement both asynchronous set and reset for stop_flag, which isn't provided with Cyclone III. The intended asynchronous set at power up (initial value) is ignored. Check, if you can change the initial value. If not, modify the design.

[Altera_Forum]

Ok..thanks so much for your reply. 

So, if i get all the pin location correct i should get the output right? but i cant hear any voice.

[Altera_Forum]

hi... 

I figure out already.Is pin location problem. thanks..

[Altera_Forum]

hai... 

when i add coefficient to the filter, the output will contain many noise. for example, (tap1<<4); What problem for this? Can any one give me some guide? Thanks..

[Altera_Forum]

hai.. 

When i add coefficient value to filter, my output contain lot of noise. I using shift method like(tap1>>5). Can any one help me or give me some guide? Thanks...

[Altera_Forum]

Hi there 

 Could you please attach NIOSII version. I am trying to roll my own, but am having problems. Would be much appreciated :)  Thanks alot !    --- Quote Start ---  Hi, The attached is a Quartus II project for 2S60 DSP kit. The design includes Verilog codes for AIC23 audio CODEC, which digitize Line-in analog and play back to Line-out.  The sample is fully controlled by a HDL state machine, but normally I use a Nios II controlled version and it’s much more flexible. If you love Nios II I will attach it.  --- Quote End ---  

[Altera_Forum]

Any chance anyone here has the Nios II code or Qsys file? I got an AD/DA card with an AIC 23 codec on it for a DE2i-150 board and I'm trying to figure out how to send and receive data. I've been attempting to do it by bit banging but I don't think it's the right way to go...