USB Blaster Rev. B compatibly with Cyclone III Starter Board???

[Altera_Forum]

I am working with the Nios II Emb. Eval. Kit Cyclone III Edition and I am trying to configure the FPGA by USB Blaster Rev. B (taken from an Cyclone II Dev. Kit). But the connection is very unstable. Around 90% of all attempts the programming fails with message "conf_done failed to go high on device 1". But the other 10% it works. So I think there might be a problem in the Board/Blaster Settings? Does anyone know if these two are compatibly to each other? Or do I have to change some setting in Quartus? Or will I have to buy a new Blaster? 

 Thanks and regards...  PS: The Blaster itself works still fine, I tried it with the old Cyclone II Board (100%)  PPS: The programming using the onboard circuitry works fine as well, but on the board my programms shall be used for there will be no onboard Blaster so I will have to use the external one...

[Altera_Forum]

I wonder, why you don't use the on-board USB-Blaster option with the Dev. Kit? However, I've been working with a USB-Blaster Rev. B on several customer boards without any problems. As a difference, the boards have an ESD protection circuit with 100 series resistors and dual schottky diodes voltage limiting diodes at all JTAG signals. It once has been said, that the TCK series resistor installed at the USB-Blaster should be increased to about 100 ohms to reduce problems with some boards.

[Altera_Forum]

As I am not very firm in all that board stuff...could you please explain a little bit more in detail how this resistor increasing should work. Will it have to be done inside the USB blaster? 

 Of course I can use the onboard circuitry but the programms I am writing will be used with another board, where there will be a Cyclone III, an MCU and some other stuff. And this board will only have a JTAG connection. So my Prof told me to use the Blaster all the time. In fact I use the onboard connector at the moment, but I will have to handle the problem until the new boards arrive.  Thanks

[Altera_Forum]

You can tell your Prof that there are known problems with the Cyclone III board and external JTAG programming, see http://www.alteraforum.com/forum/showthread.php?t=1507. According to some reports, the problem may also exist with other programming adapters, e. g. Rev. C Blaster. It must not necessary apply for your new board, it may be caused by the multiplexing circuit to on-board Blaster. 

 The TCK serial resistor with Rev. B Blaster is R14, originally a 10 ohm 0603 resistor.

[Altera_Forum]

I am a bit confused as the R14 is already a 100 Ohm resistor?! Nevertheless I have absolutely no idea where the problem could come from? So lets exclude some things... 

 - configuration scheme should have nothing to do with it (AP or PS) - unused pins should be set to input tri-stated  What about the DP-Pins? Because the QII Help tells me for me conf_done error message, that there might be a problem with the NCE pin (not at GND)???

[Altera_Forum]

If R14 has printed "100" on it, that means 10 ohms, 100 ohms would be "101" or "1000". 

Anyway, I don't know if this would help in this case, may be that some CIII Starter Boards have general problems with external JTAG connection. JTAG confifuration has always priority, there are only a few pins that could disturb JTAG programming, nCE is among them, but it has only a connection to GND through a pulldown resistor with the Starter Board. Of cause J8 must be placed to disable onboard JTAG. Users reported, that USB power would be needed in addition, but I don't see why.

[Altera_Forum]

So they mean that there also has to be a USB connection between the PC and the onboard circuitry? But why, if the LLT is disabled by JP8, there will be no leveling of the USB signal..? Anyway I will try it later on, at the moment I am willing to test every single hint :) 

 But what about the R14 again? What would it change if I switch it? The Altera support suggested to solder a 37pF capacitor to pin 1 of the JTAG connector of the board but I don't see what this should help...any suggestions?

[Altera_Forum]

Adding a capacitor has a similar effect as increasing the series resistor, if ringing clock transitions are seen at the FPGA input (and probably counted as double pulses or causing timing violation in JTAG logic), the said measures may reduce the effect. If a Altera suggestion exists, I would give it priority. 

 I also didn't understand the reports regarding USB connection technically. The observation may be wrong.

[Altera_Forum]

Well ok maybe the adding of one of these components may be our last alternative. 

 Some minutes ago I tried the stuff with the double connection...and it works? Just one question...are we sure that we programm the board now by the JTAG connector? The Blaster LED lights up while programming so normally it should be that way or am I wrong? And if I select the other Blaster (onboard) in the Hardware setup I get error message "could not access JTAG chain"...JP 8 is set of course. So does it go through the Blaster now?

[Altera_Forum]

Some minutes ago I tried the double-connection mode with an external power supply as I connected the onboard circuitry via USB cable to an I-Pod charger :)  

So now we are absolutely sure that the programming process is done by the USB Blaster.   For now my problem seems to solved for the first time. If anyone has some suggestions where the mistake might be, I would be rather thankful for writing it here so I could tell the ALTERA support...  Thanks @ all and best regards, Jens