DAC Converter

Altera_Forum · ‎04-29-2008

Hi,

I try to make a DA conversion with this board: http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html

But I am not able to make something which works well. When I check my output to an oscillo, nothing happens...:confused:

This is my VHDL code:

entity conv_DA is
port(
	clk2:in std_logic;
	output: out std_logic_vector(13 downto 0));
end entity conv_DA;
architecture behavior2 of conv_DA is
signal data: std_logic_vector(13 downto 0):="00000000000000"; --data 14 bits on the chip
Begin
	Process (clk2)
	Begin
	if clk2='0' and (clk2'event) then data<=data+'1'; --incrementation 
	end if;
	--	wait for 35 ns;
	end process;
	
	Process (data)
	Begin
	output<=data;            --update of the output
	End Process;
end architecture behavior2;

This is the VHDL source for the clock: ( I use the 100MHz clock of the board and I slow it with this code)

entity defclk is
	port(clk : in std_logic;
	     clk2 : out std_logic);
end entity defclk;
	
architecture behavior of defclk is
signal compteur: std_logic_vector(26 downto 0):="000000000000000000000000000" ;  
begin
Process(clk)
Begin
	
	if clk='0' and (clk'event) then compteur<=compteur+1; 
	end if;
end process;
clk2<= compteur(26);	-- 10ns => about 1s
	
end architecture behavior;

I think my pins are right.

I have put the jumper on the pin 5&6 on J19 for enable the clock.

If someone could help me, or could give a code which works :rolleyes:

Thanks!

Altera_Forum · ‎05-01-2008

An DAC code that works should be the DA/AD performance test provided in the factory design.

I see several points why your test may have no output. Unfortunately none of same can be seen from the information you provided:

1. I don't understand which pin or other source provides the clock to the DAC,

2. As you have a 1.5 Hz divided clock, the DAC ramp has a periof of 3 hours. It may be difficult to observe.

3. The DAC SMA output connector is transformer coupled with Mini-Circuits ADT1-1WT, that has 400 kHz lower cut-off. You can't see any LF or DC signal here.

Altera_Forum · ‎05-02-2008

Thanks for your answer

--- Quote Start ---

An DAC code that works should be the DA/AD performance test provided in the factory design.

--- Quote End ---

I see what you mean but I hane not yet foud this code because I have not installed all the cds.

--- Quote Start ---

1. I don't understand which pin or other source provides the clock to the DAC,

--- Quote End ---

I take the clock I have defined: I make an output on a pin, and I put it on J12.

My settings on j18 are PIN 7 and 8

--- Quote Start ---

2. As you have a 1.5 Hz divided clock, the DAC ramp has a periof of 3 hours. It may be difficult to observe.

--- Quote End ---

Ok, I have changed my clock:

signal compteur: std_logic_vector(11 downto 0):="000000000000" ;
clk2<= compteur(11);

--- Quote Start ---

3. The DAC SMA output connector is transformer coupled with Mini-Circuits ADT1-1WT, that has 400 kHz lower cut-off. You can't see any LF or DC signal here.

--- Quote End ---

Can I see an output signal? Now I have some pics alternatively plus and minus of the same amplitude (1 V). I do not understqnd why there is the same amplitude for a different code of 14 bits....

Or Have I to put it in an AD converter and see if my bits are right? But in this case there is a loss of data so I am not sure to have what I want to see even if the DA conversion is correct. Right?

Altera_Forum · ‎05-02-2008

If you intend to use the DAC for low frequency signals or in generally want to keep a DC component at the output, you have to modify the circuit. One option would be to remove T6 and solder a wire between T6.3 and T6.6. You get a single-ended 50 ohms output then. The same for the second channel with T5.

Altera_Forum · ‎05-05-2008

Ok,

But in fact I just want to check if I have the result I expect.

So I think I will not modify the circuit yet.

Altera_Forum · ‎05-05-2008

That's O.K., but you need to use high frequency DAC signals to pass the output transformer then.