RAM logic not inferred

[Altera_Forum]

I am running a design on Quartus and it says for 18 of my instances that it cannot infer RAM logic,what could be the possible reason ?? 

Here is the message it shows:  Info: Found 18 instances of uninferred RAM logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref0|desc_dadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref1|desc_dadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref2|desc_dadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref3|desc_dadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref4|desc_dadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref5|desc_dadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref0|desc_hadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref1|desc_hadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref2|desc_hadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref3|desc_hadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref4|desc_hadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref5|desc_hadr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref0|desc_adr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref1|desc_adr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref2|desc_adr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref3|desc_adr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref4|desc_adr" is uninferred due to illegal secondary signals in read logic  Info: RAM logic "nac_core:nac_core|rxu:rxu|rxu_dpref:rxu_dpref5|desc_adr" is uninferred due to illegal secondary signals in read logic Plz help...

[Altera_Forum]

The error message illegal secondary signals in read logic says, that your logic definition doesn't correspondend to embedded RAM hardware resources. You should show the respective code to make this point understandable.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

The problem is, that 3 RAM definition neither have an unconditional address register nor output register operation. desc_wd0 in contrast has an unconditional operated output register and can be inferred. 

The basic operation is as follows: always @(posedge clk) begin if (rxch_rd) desc_rptr <= desc_rptr + 1; rxch_dadr <= rxch_vld_i ? desc_dadr] : CSR_dump_adr; rxch_desc <= desc_wd0]; end This restriction is due to synchronous RAM hardware properties to my opinion. If it would be possible to do the rxch_vld_i selection on the registered RAM output signal, then RAM inference would work.

[Altera_Forum]

Might be you are right but when I tried only running this code then it inferred the RAM correctly ,did You notice that....

[Altera_Forum]

No, the RAM didn't infer with the original posted design. There had been some syntax errors, e. g. lost lines with end statements and a lost CR. Also the synthesis settings had to be changed to enable infernece of any size RAM. Then three RAM instances showed the error, the same as in your first post.

[Altera_Forum]

I used the full code and it inferred the RAM, 

Ok One more thing , say If I make an assignment like  reg temp <= desc_dadr[desc_rptr[1:0]]  and then the conditional statement I think it must infer RAM is it not?

[Altera_Forum]

Yes using another registered variable on address input or data output solves the problem. But it implies an additional clock cycle of pipelining. I couldn't see easily from the code, if the RAM data would be read in time then.