Error (10819)

[Altera_Forum]

Hello. 

 I want to generate a simple square wave with the system clock at 135 MHz. The "rechteck_out" vector is interpreted as "Signed(Two's complement)".   I get the following error message after compiling:   Error (10819): Netlist error at rechteck.vhd(25): can't infer register for rechteck_out[16] because it changes value on both rising and falling edges of the clock.     This is my vhdl-code:   LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all;  ENTITY rechteck IS  PORT(  clk : IN STD_LOGIC;    rechteck_out : OUT STD_LOGIC_VECTOR(20 DOWNTO 0)  ); END rechteck;  ARCHITECTURE behavior OF rechteck IS  BEGIN     PROCESS(clk)    BEGIN    IF (clk'event and clk = '1') THEN    rechteck_out <= "100000000000000000000";    ELSIF (clk'event and clk = '0') THEN    rechteck_out <= "011111111111111111111";    END IF;      END PROCESS; END behavior;     Could you please help me to solve this problem...   Thanks.

[Altera_Forum]

May be I will be alive the day when flips can work on both edges of its clk. 

You can't do that yet.

[Altera_Forum]

A physical register (flip-flop) has a single clock input. The flip-flop only latches data on a single clock edge. You cannot do double-edged clocking. 

 Jake

[Altera_Forum]

Hello tobias, 

as always Gurus are right ( otherwise they would not be gurus :) )... no way to get a F\F triggering on both clock edges... such a shame... If you have a 135MHz clock input you can generate a 67,5 MHz squarewave feeding the D input with the inverted Q output of a F\F and clocking it @ 135MHz. If you really need a 135MHz squarewave ( that is the reproduction of the input clock btw ) you can either buffer it, or feeding a PLL macrofunction IN pin with it and set a 1\1 input\output ratio, or feeding a PLL macrofunction IN pin with it and set a 1\2 input\output ratio and feeding the OUT to clock a F\F arranged as before, or ... etc. etc. I can go on with examples but I assume the concept is clear :)