LUTs vs Logic Elements/Cells

[Altera_Forum]

Hi, 

 I am currently doing initial analysis on a design. I am researching different FPGA´s regarding the required resources to implement different features.  I cannot find a method of relating the number of LUT´s used by a design and translating this into Logic Elements for the stratix range. Could you please, if possible, provide me with a good estimate for each of the stratix family?  Also if possible is it possible to use convert Logic elements from altera to logic cells in Xilinx. Are there factors that can be used between the respective families?   Basically I am looking for a general approximation of how to interchange between both LUT´s and logic elements and between logic elements and logic cells  Thank you very much for your time, Veronica

[Altera_Forum]

each Stratix III/IV ALM (LE equivalent) contains two 6-ALUTs. 

 try page 5:  http://www.altera.com/literature/hb/stx3/stx3_siii51002.pdf

[Altera_Forum]

--- Quote Start ---  Hi,   Also if possible is it possible to use convert Logic elements from altera to logic cells in Xilinx. Are there factors that can be used between the respective families?   Basically I am looking for a general approximation of how to interchange between both LUT´s and logic elements and between logic elements and logic cells     --- Quote End ---     If I can prove that LE = 1.0009 LC then Altera will make me very rich and if LE = 0.9999LC then Xilinx will... This is a very hot contentious market issue. The answer is very hard and design dependant...Your research will be most valuable source of information for us all.

[Altera_Forum]

Thank you thepancake! 

 I want to know how compare xilinx fpga with altera fpga's. Do you know a correspondence between logic elements and logic cells for the differents fpgas?   Thanks

[Altera_Forum]

kaz is on the right track. there's no easy answer for the hardware comparisons let alone once you consider the synthesizer and place/route mapping your design into hardware and meeting timing constraints.

[Altera_Forum]

Basically, you're rather comparing different names than different technologies. Although there are many detail differences, Altera and Xilinx are both using LUT to implement logic equations in their LEs/LCs or whatever you name it.

[Altera_Forum]

Thank you for you response FvM! 

 I would like to know if it possible to compare the LUTs of Altera directly with those of Xilinx, for example: Can I compare a four-input LUTs from Altera with one from Xilinx and also can I compare six-input LUTs in the same way?   Thank you   The Vero

[Altera_Forum]

If you want to find out LE/LC ratio then remember there are so many variables before you make any decision. 

 If you start from vhdl design in both cases then it goes through separate compilers/optimisers/fitters ...etc with some control given to the user. Even 3rd party compilers are vendor specific.   The best test design might be using commercial IPs in both cases, even then it is hard to narrow down the differences. Netlists are targetted and cannot help.   Apart from LE/LC there are some other differences that add to the study problem such as the various dedicated blocks, PLLs/DLL etc.   And don't forget xilinx uses LUTs as memory as well(distributed memory), while altera doesn't as far as I know.

[Altera_Forum]

in a Stratix III/IV, half the LABs are MLABs which are a little bit like distributed RAM.

[Altera_Forum]

It is possible to do some math and compare Xilinx and Altera logic utilization. But in my experience it's not going to be accurate because there are too many factors that should be taken into consideration.  

I'd recommend taking an open source design (for exampel from opencores.org) similar to yours and synthesizing it for different FPGAs.   OutputLogic

[Altera_Forum]

All, 

 Altera, in Stratix II, Stratix III and Stratix IV FPGAs, uses a logic unit is called the ALM (Adaptive Logic Element). It has an 8input fracturable LUT with 2 registers. It can be fractured efficiently to get various combinations of 6LUT, 5UTS, 4LUT, 3LUTs and 2LUTs.  Xilinx, in V5, uses the LUT-FF Pair logic unit. That is, they have a 6input LUT with one register. The one register per LUT is very inefficient when the LUT is "fractured" into smaller LUTs. In addition, the fraturability is not as efficient as the ALM.  To fairly compare the LUTs of both products, here (see below) are some white papers that outline how Altera benchmarks the logic unit. The ALM gets a 1.8x logic packing factor when compared to the LUT-FF Pair. Basically it means, that on a suite of customer designs (open ores can be included in this discussion), the ALM holds 1.8x more logic than the V5 LUT-FF pair (because the LUT-FF is not very efficient and so it needs more resources to implement the same design).  Here are some links to help you understand the concerns.  - When Altera first introduced the ALM in Stratix II, some detailed comparison was done against Virtex-5. http://www.altera.com/literature/wp/wp-01003.pdf (http://www.altera.com/literature/wp/wp-01003.pdf). This white paper still holds true as the basic ALM structure remains the same in Stratix III and Stratix IV FGPAs.  - The white paper was updated with the results for Stratix IV FPGAs (vs. Virtex-5). Here is the link: http://www.altera.com/literature/wp/wp-01088-40nm-architecture-performance-comparison.pdf (http://www.altera.com/literature/wp/wp-01088-40nm-architecture-performance-comparison.pdf)  - The overall fracturability modes of the ALM can be found here: http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/overview/architecture/stxiv-alm-logic-structure.html (http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/overview/architecture/stxiv-alm-logic-structure.html)  Regards SV

[Altera_Forum]

The way a design fits in a device is more dependent on the synthesis and fitter software than it is on the device itself. I use both Xilinx and Altera every day and I promise you that at this point in time Altera is kicking Xilinx's tail in the software arena. 

 If you want some rough idea of fit comparisons, see the opencores tests that were run: http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/performance/st3-opencores.html  So you could pick a Xilinx device that looks larger than an Altera device and most likely your compile times will increase and you will actually fit less. We struggle with this now. We have Xilinx designs that take almost a whole day to compile. We have equivalently sized Altera designs that compile in an hour.  Jake

[Altera_Forum]

This might help: 

 http://www.altera.com/literature/wp/wpstxiixlnx.pdf  Compares Stratix II vs Virtex-4, but still applicable since newer Stratix devices use same ALM structure.