pulse generation

Altera_Forum · ‎07-10-2009

Hello Forum,

I have an application that requires me to produce 2.5 - 3.5nS pulses from externally generated edges. Our target device is a Cyclone 1C6 and SW Quartus 7.2.

In the IOE description it states "there are two paths in the ioe for a combinatorial input to reach the logic

array. each of the two paths can have a different delay. this allows you

adjust delays from the pin to internal le registers that reside in two

different areas of the device. the designer sets the two combinatorial

input delays by selecting different delays for two different paths under

the decrease input delay to internal cells logic option in the quartus ii

software. when the input signal requires two different delays for the

combinatorial input, the input register in the ioe is no longer available."

So if I drive a single pin with say a 1uS rep rate signal and I want to produce a narrow pulse on both the rising and falling edges of that 1uS edge, (basically a logic delay edge detector) how does one go about defeating the Quartus tools from optimizing the path delays?

We prefer a solution that uses the Graphic/Block editor and assignment tools, as opposed to a VHDL/AHDL methods, but not opposed to the latter.

Thanks

Altera_Forum · ‎07-11-2009

Could you clarify? Do you need a produce a pulse of a fixed length or pulses of varying length. For example, does it need to sweep from 2.5 to 3.5ns or can it simply consistently generate say a 3.0ns pulse?

Jake

Altera_Forum · ‎07-11-2009

This violates all kinds of rules and normally I would never do this but here's a shot:

module edge_detect(
    input   clk_150,
    input   edge_in,
    output  edge_pulse
);
reg    edge_in_r;
assign      edge_pulse = clk_150 & ^edge_in_r;
always @(posedge clk_150)
    edge_in_r   <= {edge_in_r,edge_in};
endmodule

Jake

Altera_Forum · ‎07-11-2009

In bdf designs, LOGIGCELL symbols can be used to define delays, that are kept during synthesis. You can try with around ten logic cells.

Altera_Forum · ‎07-12-2009

to jakobjones (http://www.alteraforum.com/forum/member.php?u=2226), thanks yes I am trying to produce a single pulse and one at 3nS would be perfect. I have been using the solution that FvM suggests with logic cells in the delay path from input pin and other path direct to logic. I was trying to defeat the optimizer from balancing the 2 paths for a little more control.

I will try the code too. I appreciate all your comments.

Altera_Forum · ‎07-13-2009

Without setting additional timing constraints, no balancing would occur.