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Hello,
Does anyone know where I could find a behavioural model for the Altera PCI core (I'm using version 2.3) which implements burst read and write transfers. Many thanks DavidLink Copied
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David,
Not sure if you already figured it out but in the Altera installation dir, in a path that would be similar to this path \MegaCore\pci_compiler-v3.2.0\testbench\verilog\pci_mt32\tb_src\ you'll find the testbenches for the PCI core. In the file "mstr_tranx.v" or "mstr_tranx.vhd", you'll find the function call for burst read/write. // 32 bit memory read(Address, Number of Dwords) // mem_rd_32(32'h10000000, 4);
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