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Hello All.. I'm new to VHDL and have found myself stuck
I have problem in my code. I have created code for 8 bit shift register left.. ie my input is 11001011 then in 1st clock :- output should be :- 10010110 2nd clock :- output should be :- 00101100........to last clock 8th clock :- output should be :- 00000000 I can make a right shift using example code as follows and it works fine: Data_Int<='0' & Data_Int(7 downto 1); but when I try to following it gives me errors: Data_Int<=Data_Int(6 downto 0) & '0'; 7 errors: Warning: No output dependent on input pin "DataIP[1]" down to Warning: No output dependent on input pin "DataIP[7]" and when I simulate it Data_Int just goes to 1 and stays there. Here's my full code listing. Any help would be appreciated thanks. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY shift IS PORT( Clk : IN std_logic; DataIP : IN std_logic_vector(7 downto 0); DataOP : OUT std_logic; load : IN std_logic; rst : IN std_logic; shift_out : IN std_logic); END shift; ARCHITECTURE behavioural OF shift IS SIGNAL Data_Int : std_logic_vector(7 downto 0); --internal signal BEGIN PROCESS(Clk,load,shift_out,Data_Int) BEGIN IF(Clk'EVENT AND Clk='1')THEN IF(rst='1')THEN Data_Int<="00000000"; --if reset clear Data_Int and DataOP ELSIF(load='1')THEN Data_Int<=DataIP; --if load then load data from external ELSIF(shift_out='1') THEN Data_Int<='0' & Data_Int(7 downto 1); --if shift then shift it right --Data_Int<=Data_Int(6 downto 0) & '0'; --if shift then shift it left END IF; --ELSE -- Data_Int<=Data_Int; --all other conditions END IF; --could put DataOP<=Data_Int(0); here END PROCESS; DataOP<=Data_Int(0); --signal assignment outside process END behavioural;Link Copied
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Figured it out.
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